In integrated circuit (IC) fabrication, understanding and optimizing process interactions and variability is critical for swift process integration and performance enhancement, especially at dimensions ≤0.25μm. We present here an approach to address this challenge, and we apply it to improve the process design for two critical modules in a typical CMOS IC process—salicide and source/drain. Together, these modules impact the silicide-to-diffusion contact resistance (Rc), and the gate sheet resistance (Rs); which, in turn, significantly affect transistor series resistance and circuit delays respectively. In our approach, we have investigated a process domain consisting of both silicide and source/drain process variables; and we have developed a quantitative framework for analysis and optimization, along with qualitative insight into underlying the physical mechanisms. We demonstrate that the transistor drive current (Id) improves by ≈5‥, and circuit performance, as measured by the figure-of-merit (FOM), by ≈4‥. This improvement is significant, and an added benefit is that other transistor characteristics such as effective channel length, off-current, substrate current etc. are affected minimally. Finally, we use this approach to optimize trade-offs such as Rc vs Rs and performance vs manufacturability; thus enabling manufacturable processes that meet the requirements for high performance.

A modular approach to CMOS process development requires an understanding of individual process modules (channel, gate etc.) and their interactions. The reverse short channel effect (RSCE) in NMOS devices is one such interaction between the channel and source/drain (S/D) modules. Similarly the interaction between the S/D and silicide modules affects the contact and gate sheet resistance. This paper presents (a) an investigation of the effects of S/D processing (As and P implant conditions) on the RSCE, (b) effects of S/D and silicide processing on the contact and gate sheet resistance, (c) the use of an integrated system to optimize process modules and their interactions and (d) the validity of the modules and system in process development by obtaining a 4% improvement in drive current of a 0.25 micron NMOS device.

As CMOS technologies are scaled to 0.10 μm and beyond, self-aligned silicide (salicide) processes find difficult challenges. As junction depths and linewidths are scaled, achieving both low sheet resistance and low contact resistance maintaining low diode leakage becomes increasingly difficult. In this paper we present studies of Ti and Co salicide processes implemented into a 0.10 μm CMOS technology. We show that both for Ti and Co, the optimization of RTP parameters plays a crucial roll in achieving a successful implementation. For Co salicide, optimization of RTP conditions results in elimination of shallow junction leakage (its main scaling problem). Two-step RTP and one-step RTP Ti salicide processes are compared, showing the advantages of one-step RTP. The RTP process windows for low resistance narrow gates (the main scaling issue for Ti salicide) are analyzed. Processes with pre-amorphization, with Mo doping and with a combination of both are compared. An optimal process using Mo and preamorphization implants and one-step RTP is shown to result in excellent device characteristics and low resistance to 0.06 μm gates.

In recent years, we have developed rapid photothermal chemical vapor deposition (RPCVD) technique. In RPCVD, photons with wavelength between 100–400 nm irradiate the side of the substrate where chemical reactions take place. RPCVD provides materials with minimum microscopic defects and minimum thermal and residual stress. Due to these features and low processing time and low processing temperature capabilities, RPCVD is ideal for process integration and manufacturibility. In this paper we have presented the results of high K and low K dielectrics. Detailed electrical, structural, characterization, and stress measurements combined with reliability of data indicate that RPCVD has the potential of meeting advanced manufacturing needs of semiconductor and other related industries.

The sol-gel system iron triethoxide - tetraethylorthosilicate (TEOS) with the Fe/Si atomic ratio ranging from 0 to 1 has been investigated. Our study leads to the conclusion that the annealing method of the hydrolyzed precursor film determines the type of solid film formed. Annealing by Rapid Thermal Processing (RTP) with its high heating and cooling rates yields amorphous, glassy iron silicate films. These films result from polycondensation reactions between Si-OH and Fe-OH groups of the hydrolyzed precursors forming Fe-O-Si and Si-O-Si bonds. These bonds show a characteristic vibration band in FTIR spectra, which is most intense for Fe/Si = 1, and shifts for increasing Fe/Si ratio from 1073 down to 965 cm-1.

The iron silicate film with Fe/Si =1 obtained by RTP displays an optical absorption band around 320 nm, which indicates that Fe3+-ions have a tetrahedral coordination similar to the Si4+-ions in Si02 and glass with tetrahedrally coordinated silicon and iron ions linked by bridging oxygen atoms. The films, typically 0.1 μm thick, annealed by RTP have a smooth, mechanically hard surface. This glassy structure can be formally presented as FeSiOx. Conventional furnace heating with low heating/cooling rates yields nanocrystalline films with predominantly Si-O-Si bonding in grains with sizes below 40 nm. More structural and chemical investigation is needed to elucidate the details of the structure and the formation mechanism of the amorphous compound, but we can conclude that the cooling rate has a direct effect on the degree of non-crystallinity of the compound. The high cooling rate of RTP will retain the Fe-O-Si bonds formed in a state of inequilibrium, and “quench” them in an amorphous, metastable glass compound, whereas slow cooling gives rise to nanocomposite film formation.

In various device fabrication processes, such as in metal gate and low resistance word line fabrication, one needs to be able to oxidize Si without oxidizing metals present. We developed such a process using a combination of H2 and O2 in the H2 rich regime. The process developed is safe and is production worthy with excellent uniformity.

When carrying out the selective oxidation using H2/O2, a high Si oxidation rate is preferred which requires a high oxygen concentration. At the same time, the increase in metal sheet resistance, if any, must be small. We found that with an oxygen concentration as high as 20%, the increase in W sheet resistance is small. We present data on the oxidation rate of Si under different conditions as well as the selectivity of the process with respect to W and WN.

Hemispherical grained (HSG) polycrystalline-silicon surfaces are used in DRAM manufacturing to enhance cell capacitance by increasing the surface area of the capacitor electrodes. We study the formation of HSG poly-silicon in a Rapid Thermal CVD (RT-CVD) cluster tool with in-situ native oxide removal. Compared to conventional ex-situ wet cleaning procedures, use of the in-situ native oxide removal both decreases the process temperature at which HSG formation occurs and increases the width of the temperature window within which desirable HSG layers are formed.

In this paper, we report new results on tungsten silicide ( WSix ) degradation during furnace oxidation. During Poly-oxidation step performed after gate patterning, a deformed oxide is grown on WSix /Poly gate lines giving rise to protrusions (or nodules) at the interface between the two materials. Different parameters were evaluated including oxidation conditions, WSix deposition parameters, WSix capping dielectric and thermal treatments. The first conclusion of these experiments is that protrusions can be eliminated if Si/W ratio in as-deposited material is greater than 2.6 when no furnace thermal treatment is done on the WSix. /Poly stack before furnace oxidation. The more important conclusion is that addition of a Rapid Thermal pretreatment with a temperature range between 700 and 1000 degrees done just after WSix /Poly etch and before furnace oxidation eliminates totally the defects. Both results can be explained with internal stress reduction in the WSix film which lead to suppression of accelerated oxidation kinetics at the interface between polysilicon and WSix films during furnace oxidation after gate patterning.

We have determined the process capability of Low Pressure (Rapid Thermal) Chemical Vapor Deposition (LP(RT)CVD) of epitaxial Si/SiGe/Si stacks for heterojunction bipolar transistors (HIBTs). The transistor parameters primarily influenced by the epitaxial characteristics were measured for 600 identically processed 4” wafers. The results demonstrate that it is possible to control accurately the epitaxial process for a 25 nm thick graded SiGe base profile with 20 % Ge and very narrow B doping (5 nm). The pipe limited device yield of about 90 % for an emitter area of 104 μm2 indicates a very low defect density in the epitaxial layer stack. The process capability indices determined from about 40,000 data points demonstrate the stability and capability of the LP(RT)CVD epitaxy with regard to manufacturing requirements.

We demonstrate that SiO2 cap rapid thermal annealing in ultra-thin p-type InGaAs/InP quantum wells can be used to produce large blue shifts of the band edge. A substantial bandgap blue shift, as much as 292.5 meV at 900°C has been measured and the value of the bandgap shift can be controlled by the anneal time. Theoretical modeling of the intermixing effect on the energy levels is performed based on the effective bond-orbital method, and we obtain a very good fit to the photoluminescence data. Compared to the as-grown detector, the peak spectral response of the annealed detector was shifted to longer wavelength without any major degradation in the responsivity characteristics.

Hydrogenated amorphous silicon (a-Si:H) films which were deposited by plasma enhanced chemical vapor deposition (PECVD) have been recrystallized by the two-step rapid thermal annealing (RTA) employing the halogen lamp. The a-Si:H films evolve hydrogen explosively during the high temperature crystallization step. In result, the recrystallized polycrystalline silicon (poly-Si) films have poor surface morphology. In order to avoid the hydrogen evolution, the films have undergone the dehydrogenation step prior to the crystallization step.

Before the RTA process, the active area of thin film transistors (TFT's) was patterned. The prepatterning of the a-Si:H active islands may reduce the thermal damage to the glass substrate during the recrystallization. The computer generated simulation shows the heat propagation from the a-Si:H islands into the glass substrate. We have fabricated the poly-Si TFT's on silicon wafers. The maximum ON/OFF current ratio of the devices was over 10.