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A Study of Transistor Optimization in A 0.25 Micron Cmos Flow Using Source/Drain and Silicide Process Modules and Their Interactions

Published online by Cambridge University Press:  10 February 2011

K. Vasanth ,
P. Apte ,
J. Davis ,
S. Saxena ,
R. Burch ,
S. Rao  and
P. K. Mozumder
K. Vasanth
Affiliation:
Silicon Technology Development, Texas Instruments Inc., P.O. Box 650311, MS 3704, Dallas Tx 75243. vasanth@spdc.ti.com
P. Apte
Affiliation:
Silicon Technology Development, Texas Instruments Inc., P.O. Box 650311, MS 3704, Dallas Tx 75243. vasanth@spdc.ti.com
J. Davis
Affiliation:
Silicon Technology Development, Texas Instruments Inc., P.O. Box 650311, MS 3704, Dallas Tx 75243. vasanth@spdc.ti.com
S. Saxena
Affiliation:
Silicon Technology Development, Texas Instruments Inc., P.O. Box 650311, MS 3704, Dallas Tx 75243. vasanth@spdc.ti.com
R. Burch
Affiliation:
Silicon Technology Development, Texas Instruments Inc., P.O. Box 650311, MS 3704, Dallas Tx 75243. vasanth@spdc.ti.com
S. Rao
Affiliation:
Silicon Technology Development, Texas Instruments Inc., P.O. Box 650311, MS 3704, Dallas Tx 75243. vasanth@spdc.ti.com
P. K. Mozumder
Affiliation:
Silicon Technology Development, Texas Instruments Inc., P.O. Box 650311, MS 3704, Dallas Tx 75243. vasanth@spdc.ti.com
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Abstract

A modular approach to CMOS process development requires an understanding of individual process modules (channel, gate etc.) and their interactions. The reverse short channel effect (RSCE) in NMOS devices is one such interaction between the channel and source/drain (S/D) modules. Similarly the interaction between the S/D and silicide modules affects the contact and gate sheet resistance. This paper presents (a) an investigation of the effects of S/D processing (As and P implant conditions) on the RSCE, (b) effects of S/D and silicide processing on the contact and gate sheet resistance, (c) the use of an integrated system to optimize process modules and their interactions and (d) the validity of the modules and system in process development by obtaining a 4% improvement in drive current of a 0.25 micron NMOS device.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 525: Symposium W – Rapid Thermal & Integrated Processing VII , 1998 , 325
Copyright
Copyright © Materials Research Society 1998

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References

REFERENCES

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