In integrated circuit (IC) fabrication, understanding and optimizing process interactions and variability is critical for swift process integration and performance enhancement, especially at dimensions ≤0.25μm. We present here an approach to address this challenge, and we apply it to improve the process design for two critical modules in a typical CMOS IC process—salicide and source/drain. Together, these modules impact the silicide-to-diffusion contact resistance (Rc), and the gate sheet resistance (Rs); which, in turn, significantly affect transistor series resistance and circuit delays respectively. In our approach, we have investigated a process domain consisting of both silicide and source/drain process variables; and we have developed a quantitative framework for analysis and optimization, along with qualitative insight into underlying the physical mechanisms. We demonstrate that the transistor drive current (Id) improves by ≈5‥, and circuit performance, as measured by the figure-of-merit (FOM), by ≈4‥. This improvement is significant, and an added benefit is that other transistor characteristics such as effective channel length, off-current, substrate current etc. are affected minimally. Finally, we use this approach to optimize trade-offs such as Rc vs Rs and performance vs manufacturability; thus enabling manufacturable processes that meet the requirements for high performance.