Oxynitridation in nitric oxide of commercial 5 nm and 13 nm oxides is investigated, as well as reoxidation steps. The results are discussed in terms of atomic transport mechanisms and modification of interfacial microstructure. Atomic transport is studied through the use of isotopic tracing and nuclear reactions analyses (NRA): we measured the atomic areal densities (14N, 15N, 16O, 18O) in the films and the concentration depth profiles of the heavy and stable isotopes (15N, 18O) with near surface subnanometric resolution. To scan the evolution of the interfacial microstructure, Pb0 centers concentrations were measured by electron paramagnetic resonance spectroscopy (EPR), after each treatment step. The previously proposed mechanisms for NO oxynitridation of silica are confirmed: i) the NO molecules diffuse via interstitial sites, without reaction with the lattice, before reacting with the dielectric/Si interface; ii) at the external surface region, oxygen exchange is observed due to a step-by-step motion of network oxygen atoms induced by the presence of network defects. During reoxidation in O2 neither loss or observable redistribution of nitrogen is evidenced. For the 13-nm thick film, in the external surface region, the oxygen exchange is seen to be more effective than in the case of silica (or silicon) oxidation: that is O2 is more reactive on NO-nitrided silica than on pure silica. The concentration of Pbo centers decreases after the NO thermal step and increases again after the further reoxidation step.

This work surveys some of our recent experimental and theoretical advances in charge pumping for the electrical characterization of interface traps present in MOSFET architectures. The first part of this paper is devoted to an improved time-domain analysis of the charge pumping phenomenon. This approach presents the main advantage to use the same formalism to describe the charge pumping contribution of a single trap or a continuum of traps at the Si-SiO2 interface. The implications for deepsubmicron MOSFET characterization are illustrated. Some experimental aspects are then presented, including the adaptation of the technique to ultra-thin oxides, non-planar oxides and DRAM memory cells. Finally, recent charge pumping characterization results are reported concerning the electrical behavior of the Si-SiO2 interface submitted to particular technological treatments, electrical and radiation stresses, or post-degradation anneals.

Defects in thermal oxides were investigated by a photoluminescence technique. Thermal oxides with a thickness of 100 nm grown either by dry or wet oxidation were studied. A broad PL band at 2-4 eV was observed for both dry and wet oxides. Effects of annealing under vacuum or in atmospheres of Ar or N2 on the PL were also examined. The PL intensity was enhanced for the case of wet oxide by vacuum annealing at 700 °C. High-temperature anneal above 750 °C without O2 further generated PL centers for both dry and wet oxides. The formation mechanism of the PL centers will be discussed in terms of the decomposition of oxide at Si/SiO2 interface.

This paper discusses the evolution in the degradation and breakdown behaviour of ultra-thin oxides when scaling the oxide thickness into the sub-4 nm range for future CMOS technology generations. It will be shown that changes in the breakdown statistics, which can be explained by a percolation model for breakdown, lead to an increased area dependence of the time-tobreakdown. This has to be taken into account when predicting the oxide reliability. Also the impact of the test methodology, the relevance of a so-called polarity gap in the charge-tobreakdown and its consequences for reliability testing, are highlighted. Moreover, a strong increase in the temperature dependence of breakdown, especially for sub-3 nm oxides, is demonstrated and the impact of temperature on trap generation and critical trap density at breakdown is discussed. Finally it is shown that the combined effects of all these phenomena might lead to oxide reliability becoming a potential showstopper for further technology scaling.

This paper describes the electrical and physical characteristics of ultrathin Jet Vapor Deposited (JVD) Silicon Oxynitride films. Capacitance-Voltage measurements indicate an equivalent oxide thickness (EOT) of less than 2 nm, taking into account the quantum-mechanical correction. These films have leakage currents almost two orders of magnitude lower than thermal oxide of the same equivalent thickness. Measurements on NMOSFETs with 0.15 μm of channel length demonstrate excellent electrical properties, including high drive currents (∼0.5 mA/μm @ Vd=Vg–Vt=l.5 V), low sub-threshold swings (∼72 mV/decade), and high transconductance (∼0.36 mS/μm @ Vd=1.5 V). These films were also analyzed using a variety of physicochemical methods, including Total X-ray Fluorescence (TXRF), Atomic Force Microscopy (AFM), Nuclear Reaction Analysis (NRA), Low Energy (500 eV) Secondary Ion Mass Spectrometry (SIMS), and Transmission Electron Microscopy (TEM). Surface metal concentrations of less than 1011 atoms/cm2 were measured from the TXRF analysis. The microroughness values for these films varied between 0.15 – 0.17 nm as measured by AFM. Low energy (500 eV) SIMS and NRA indicate high [N] near the top as well as throughout the bulk of the film, and a significant amount of [O] near the top of the film. High Resolution TEM pictures show a very uniform film with a physical thickness of 2.8 ± 0.1 nM, which yields an effective dielectric constant of 5.5, consistent with these types of oxynitride films.

Direct tunneling limits aggressive scaling of thermally-grown oxides to about 1.6 nm, a thickness at which the tunneling current. Jg, at one volt is ∼1 A/cm2. This paper presents results that demonstrate that stacked gate dielectrics prepared by remote plasma processing that include i) ultra-thin nitrided SiO2 interfacial layers, and ii) either silicon nitride or oxynitride bulk dielectrics can extend the equivalent oxide thickness, EOT, to 1.1-1.0 nm before Jg, > 1 A/cm2.

The dielectric breakdown is an irreversible and transient process, and it is difficult to understand its dynamic characteristics. We notice that the post-breakdown electrical properties of silicon dioxide films may include much information on the dielectric breakdown mechanism. First, the resistance of silicon dioxide films after the dielectric breakdown is statistically investigated, and then this analysis is applied to differentiate the hard- from the soft-breakdown. In particular, we discuss the critical dependence of the boundary between the hard- and softbreakdown on the discharging time constant as well as the discharging energy at the breakdown, concerning the formation of the conductive filament in the insulator silicon dioxide films. It should be noted that the ratio of the soft- to the hard-breakdown changes in terms of the statistical distribution in the case that the growth parameters and the measurement conditions are changed. In partcular, the external inductance effect to modify the discharging time constant in the MOS circuit is discussed. The thickness limitation of the silicon dioxide film in the roadmap is in this transition region, and this fact will be of essential importance in the assessment of the reliability and the process control of silicon device fabrication in sub-5nm silicon dioxide regime.

A Monte Carlo simulation of wear-out process in thin silicon dioxide films is performed to investigate the correlation between the electron trap distribution and the dielectric breakdown. Non-uniformity of the trap generation and its dependence on the stress conditions are monitored by the measurements of the charge centroid. In order to include these experimental observations into Degraeve's percolation model [IEDM Tech. Dig., pp.863-866 (1995)], we introduce exponential trap profiles decaying from the Si/SiO2 interface. Our new model successfully reproduces critical threshold voltage shifts from the information about critical charge centroids for various stress conditions. Finally, as a reasonable explanation of the stress dependent breakdown properties, we suggest that the bond strain caused by lattice mismatch at the interface is accelerated by the electric field.

For sub-5 nm oxides there are two different stages for breakdown; soft breakdown (SBD) and hard breakdown (HBD). It has been shown that both SBD and HBD exhibit the same statistics. Therefore, the physical mechanism governing them is the same. The major difference between them is the energy transferred from the capacitor to the localized conducting path. In this paper, a simple equivalent circuit is proposed to explain the effect of the measurement technique, oxide thickness, and test structure area on the detection of soft breakdown. Also an inelastic quantum tunneling model is proposed to discuss the current-voltage characteristics after SBD. The model is also successful in explaining the temperature dependence of SBD IV characteristics.

Corona charging in air combined with non-contact oxide charge measurement with a contact potential difference probe provides an unique possibility for fast monitoring of electron tunneling characteristics without preparation of MOS capacitors. It has also been found tha corona charging of thin oxides in the tunneling range is very effective in generating stressinduced leakage current. In this work we demonstrate the sensitivity of the corona stressinduced leakage current magnitude to gate oxide integrity defect density. The experimenta results cover three of the most common gate oxide integrity defects, namely: 1 – the defect induced by heavy metals (Fe.Cu) at a practically important low concentration range of 1×1010 to 1×1011 atoms/cm3: 2 – the defects originating from interface roughness and 3–the defects related to crystal originated particles.

At low corona stress fluence, these defects play no role in the tunneling characteristics which follow ideal Fowler-Nordheim characteristics for oxides 50Å or thicker and a contribution from a direct tunneling current for thinner oxides. At high corona stress fluences, gate oxide integrity defects control the magnitude of stress-induced leakage current measured at constan oxide field. It is suggested that the gate oxide integrity role is associated with the enhanced rate of the trap generation during stress. It is noted that the present findings employ a novel methodology for gate oxide integrity monitoring based on corona charging and contact potential difference measurement.

Conventional superlattices are formed with repeating a basic period consisting of a heterojunction between two materials. A new type of superlattice are formed by replacing the heterojunction between adjacent semiconductors with semiconductor layers separated by adsorbed species such as oxygen atoms; and CO, molecules, etc. This new type of superlattice, SAS, semiconductor-atomic-superlattice, fabricated epitaxially, enriches the present class of heterojunction superlattices and quantum wells for quantum devices. The Si growth beyond the adsorbed monolayer of oxygen is epitaxial with fairly low defect density. At present, such a structure shows stable electroluminescence and insulating behavior, useful for optoelectronic and SOI (silicon-on-insulator) applications. SAS may form the basis of future all silicon ‘superchip’ with both electrons and photons.

Photoconductance spectroscopy was used to probe the effects of quantum confinement in nanocrystalline (nc)-Si/amorphous (a)-SiO2 superlattices (SLs). A Metal-Oxide-Semiconductor (MOS)-like structure with the nc-Si SL incorporated in the oxide was fabricated to study charging/discharging processes in Si nanocrystals. The fine structure observed in photoconductance spectra at low temperatures was interpreted in terms of singularities in the carrier density of states, possibly due to energy quantization. In addition, a low-resistance sample exhibited photocurrent oscillations with a frequency of several kHz, which could be a manifestation of sequential resonant carrier tunneling in the nc-Si/a-SiO2 SL.

The stress distribution in Si(111)/Si3N4(0001) and Si(111)/a-Si3N4 nanopixels are studied using molecular dynamics simulations on parallel computers. Bulk Si is described by the Stillinger-Weber potential and Si3N4 is represented by a combination of two- and three-body interactions that include steric, charge transfer, polarizability and covalent forces. The charge transfer at the interface is extracted from self-consistent electronic structure calculations. The molecular dynamics simulations for Si(111)/a-Si3N4 nanopixels involve two pixel sizes: 25nm and 54 nm (the systems consist of 3.7 million and 10 million atoms, respectively). In both systems we find stress domains at the interface, which extend into the silicon substrate. The nature of the stress domains is discussed.

Nanocluster memories are promising for future non-volatile memory applications. In this work thin SiO2 films were implanted with Ge+ and Si+ and annealed subsequently. Charge storage effects of the MOS capacitors have been studied through I-V and high frequency C-V measurements. Positive voltage pulses lead to a positive flatband voltage shift of the C-V curve. Detrapping by applying negative voltage pulses leads to a negative shift. The achieved programming window using 6 V / 100 ms pulses for Ge based structures is higher than that for Si (2.0 V vs. 0.2 V). However the retention times for Si based memories are longer. For dedicated process parameters microstructural investigations (RBS, XTEM) of Ge+ implanted SiO2 layers showed two bands of clusters, one near the interface SiO2/Si and one in the center of the SiO2 layer.