Crafting Moore’s Plot

Gordon Moore was relatively new to semiconductor technology when he devised Moore’s plot over several years in the early to mid-1960s. After earning a PhD in chemistry at the California Institute of Technology (Caltech), he joined Shockley Semiconductor Laboratory, Silicon Valley’s first semiconductor start-up, in 1956. Rebelling against William Shockley, Shockley Semiconductor’s founder, he established Fairchild Semiconductor with Robert Noyce and six other scientists and engineers the following year. At Fairchild, Moore quickly established himself as the firm’s technical leader, becoming the head of its research laboratory. Under his leadership, the laboratory originated fundamental innovations such as the planar process and the planar integrated circuit.Footnote ⁶

In 1963, Moore wrote a seminal chapter on integrated circuit technology and the economics of semiconductor manufacturing for a volume on microelectronics edited by Edward Keonjian. This book reviewed different approaches to electronics miniaturization, including hybrid circuits, thin-film circuits, and functional devices. In his contribution to the volume, Moore aimed at convincing others in the industry that integrated circuits offered the cheapest avenue to make electronic devices and systems smaller. This was a novel argument at the time, as the general consensus among engineers was that miniaturization added to the cost of electronics. To make the case that microcircuits would make electronics inexpensive, Moore contended that the cost per electronic function would decrease as integrated circuit complexity increased. Because of this dynamic relationship, Moore predicted that “the amount of circuit function to be put economically in a single functional block will increase rapidly. This in turn will further contribute to cost and reliability improvements in systems.”Footnote ⁷

To support this argument, Moore made a detailed analysis of the economics of semiconductor production. He noted that the fabrication cost of an integrated circuit was highly dependent on yield, the percentage of salable microchips coming out of the manufacturing line. In turn, Moore argued, yield depended on the size of the die, the piece of silicon crystal on which one patterned a single integrated circuit. The smaller the die, the likelier it was that it would not be impaired by “bad spots” such as minute defects in the dioxide layer protecting the silicon crystal. By decreasing the size of the die through process improvements, one could reduce the incidence of these “bad spots” and, therefore, increase yield and lower cost. “As the complexity is increased,” Moore argued,

In short, integrated circuits were poised to become dramatically cheaper than equivalent circuits made of discrete components, and the reduction in their cost would be dictated by evolving processing capabilities.

Making the most of this insight, starting in 1963, Moore reoriented his laboratory toward integrated circuit technology. He requested that scientists and engineers working in his laboratory design and fabricate increasingly complex integrated circuits. He also funded this activity very heavily. Harry Sello, the head of the laboratory’s process and materials section, later remembered that Moore would regularly ask him and other researchers to develop integrated circuits with more and more transistors. As Sello put it, Moore “pushed us to go back to the lab, reduce the imperfections in silicon crystals, and improve the manufacturing process. This drove us into better production capability.”Footnote ⁹ As a result, Fairchild introduced increasingly complex integrated circuits to the market. By 1965, its most advanced chip had fifty transistors.Footnote ¹⁰

However, the firm’s integrated circuits did not sell well. Electronics engineers were hesitant to employ microchips in their devices and systems. To persuade engineers to adopt the new technology, Moore gave several talks on the future of integrated circuits at professional meetings in 1964. The following year, he published an article on microchips, titled “Cramming More Components onto Integrated Circuits,” in Electronics, a trade magazine. In this piece, he outlined the argument about the economics of microchip manufacturing he had presented in Keonjian’s volume two years earlier. However, in a departure from his earlier piece, he quantified the complexity increase he had envisioned in 1963. He produced a plot, later known as “Moore’s plot,” showing the number of components per microchip as a function of time (figure 1). To create this plot, Moore used the component counts of the most complex chips Fairchild had introduced to the market over the previous three years. As he created the plot, Moore realized, for the first time, that since the initiation of integrated circuit technology, the number of components in Fairchild’s chips had doubled every year.Footnote ¹¹

Figure 1 Moore’s plot, 1965.

Source: Gordon Moore, “Cramming More Components onto Integrated Circuits,” Electronics, April 19, 1965, 116. @2006 IEEE, reprinted with permission.

With this plot, Moore went further than quantifying his success as a research manager. He made an important addition to the graph by inserting a dotted line showing that the annual doubling of components per chip would continue for another ten years. This was a bold prediction. It was also a masterstroke of marketing. To persuade electronics engineers to employ microchips in their designs, Moore argued that circuit complexity would increase exponentially and that the most advanced integrated circuits would have 65,000 transistors in 1975. This exponential increase, Moore contended, would revolutionize electronics. It would dramatically reduce the cost of electronic functions. It would also make new types of electronic devices such as “home computers” possible. Furthermore, Moore asserted that there were no fundamental physical limitations to the trend toward greater complexity. Only good engineering was needed. “The future of integrated electronics,” Moore asserted, “is the future of electronics itself. The advantage of integration will bring about a proliferation of electronics, pushing this science into many new areas.”Footnote ¹²

Moore’s article was widely read. It soon became part of a debate on the future of miniaturization. On the one hand, research managers at Bell Labs openly doubted that microchips would significantly lower the cost of electronic systems. The more complex the integrated circuit, they argued, the more likely it was that one or more of its elements would be nonfunctional. As a result, the yield of the integrated circuit as a whole would drop to zero, making the technology uneconomical. Similarly, many IBM managers and engineers were skeptical about Moore’s contention that improvements in processing capabilities would drive microchip costs down. They favored another approach to miniaturization—hybrid circuits—for their new line of computers, System/360. Other engineers in the electronics industry argued that Moore’s prediction was based only on a few data points and that, as a result, its predictive power was nil. They also contended that the plot was an artifact of the observer, as it was based exclusively on Fairchild’s microchips.Footnote ¹³

But Moore’s plot and his attendant prediction on the future of integrated circuits also had their supporters, including within Bell Labs and the research laboratory of IBM. None were more vocal than Patrick Haggerty and other Texas Instruments (TI) executives. Like Moore, they contended that microchips would make “impressive contributions” to electronic systems by “removing limitations of reliability, cost, and complexity.”Footnote ¹⁴ For example, in an article published in 1966, Richard Petritz, the director of TI’s semiconductor research and development laboratory, predicted the advent of large-scale integrated (LSI) circuits, chips with thousands of transistors, and he forecasted that within ten years, integrated circuit density would reach a million transistors per square inch. He also presented his own version of Moore’s plot, which exhibited a slower rate of complexity increase than Moore’s. Like Haggerty and Petritz, executives at Motorola pushed for constant increases in chip complexity in the second half of the 1960s.Footnote ¹⁵

It was at Fairchild that Moore’s article had the greatest impact. Starting in 1965, Moore used his plot as a planning tool to guide process and product development and allocate financial and engineering resources within his laboratory. He instructed researchers to increase chip complexity by a factor of two every year. By doing so, Moore surmised, Fairchild would stay ahead of its competitors and remain on top of Moore’s band. This was important for economic reasons. The more complex the microchip, the more profitable it became. With the profits made on high performance chips, Fairchild could reinvest in the development of advanced products and processes. In contrast, competing firms such as Sylvania and General Electric that were positioned significantly lower in Moore’s band were in a precarious financial situation, so much so that many left the business in the late 1960s and early 1970s. The plot was not only a marketing and technology planning tool. It was also a competitive weapon that would allow Fairchild to commercialize the highest performance chips at the lowest possible cost and stay in the business over the long run.Footnote ¹⁶

Promoting Moore’s Plot

In the mid-1960s, Moore made another inventive use of his plot. He employed it to spot new technological and entrepreneurial opportunities. In 1966, Moore and his Fairchild colleague, Robert Noyce, noticed that engineers would soon be able to put enough transistors on a die to fabricate a new type of integrated circuit, semiconductor memories. This realization and internal conflicts at Fairchild Camera, Fairchild Semiconductor’s parent company, led Noyce and Moore to leave Fairchild and form Intel in 1968. The primary focus of the new firm was to design, produce, and market memory circuits that would replace magnetic cores in computer terminals, minicomputers, and mainframes. Noyce and Moore aimed to commercialize the highest performance chips and sell them at a high price. As soon as these circuits were copied by other corporations, they would cease producing them and introduce more advanced products to the market.Footnote ¹⁷

This commercial strategy was predicated on adhering to Moore’s plot. Intel had to double transistor counts every year in order to stay ahead of its competitors. This objective soon became a fundamental expectation at the firm. To drive the growth in chip complexity, Moore and Noyce put great emphasis on the development and continuous improvement of advanced manufacturing processes. For example, in the late 1960s, they bet their corporation on the development of the silicon gate process. This process relied on polysilicon to form the gates of MOS transistors. It reduced the space between components, thereby enabling the cramming of more transistors onto the same die. Intel’s engineers were among the first to adopt projection lithography, a technique that helped produce smaller patterns onto silicon dies. With these processes, Intel’s factories produced the most complex microchips, those with the most transistors, in the first half of the 1970s.Footnote ¹⁸

Moore’s plot also oriented product design. It enabled Intel’s managers to determine the complexity they had to achieve with their microchips at any given time. Leslie Vadasz, the head of memory engineering in the late 1960s and early 1970s, later reminisced that Moore’s plot “was a sanity check for the product we were designing. As you went along with the design, you had a transistor budget. You looked at it. If you were way off for whatever reason, you took a second look.”Footnote ¹⁹ Another important usage of the plot was its employ in purchasing decisions regarding materials and manufacturing tools. “When you worked with equipment companies and looked at the capability of their equipment,” Vadasz added, “you took Moore’s [plot] into account. Moore’s [plot] was the guide.”Footnote ²⁰

The plot was a living instrument, repeatedly tweaked by Moore and his associates at Intel. In the late 1960s and 1970s, Moore regularly updated the graph, adding Intel’s chips as the new data points on the curve. He also integrated the development of novel device structures and circuit types into his plot. More importantly, in 1975 Moore revised his plot. In a talk presented at a meeting of the Institute of Electrical and Electronics Engineers (IEEE), he argued that the trend he had identified ten years earlier would soon slow down. He predicted that starting in 1980, the number of transistors per microchip would double every two years, instead of every year. This was a point he reiterated in talks he presented on the future of integrated circuit technology at professional and industry meetings over the next four years. Moore made this forecast on the basis of the growing difficulties Intel’s engineers encountered in producing more and more complex integrated circuits. The smaller the silicon structures, the more prominent the contamination problems became. With the silicon gate process and its subsequent incarnations, Intel’s engineers had also reduced the space between transistors to the point where there was no space left. According to Moore, only two avenues remained for increasing the number of transistors on the same chip: making the die bigger and reducing the size of the transistors.Footnote ²¹

In the 1970s, Moore and his Intel colleagues heavily promoted Moore’s plot. The plot appeared prominently in talks by Moore, Noyce, Andrew Grove, and other Intel managers. For example, in the mid- and late 1970s, David House, the firm’s marketing manager for microprocessors and, later, the general manager of its microprocessor division, started every presentation to customers with a discussion of Moore’s plot. In these promotional efforts, Intel’s leadership was greatly helped by Carver Mead, a faculty member at Caltech and a friend and business associate of Moore. In the late 1960s and early 1970s, Mead gave a series of talks at universities and corporate research laboratories where he, in his own words, “crusaded” for Moore’s plot. He argued that it was possible to scale down transistors to much smaller dimensions and that, as these transistors scaled, all their characteristics would significantly improve. In 1972, Mead and his doctoral student Bruce Hoeinesen published two articles in Solid-State Electronics in which they explored the physics of growing chip complexity. This analysis led them to claim that the industry had ten more years of exponential complexity increase in front of it and that by 1980 integrated circuits would have ten million transistors per square centimeter.Footnote ²²

Intel’s managers and their academic allies publicized Moore’s plot very heavily, because many in the industry thought that the trend toward greater integration was about to end (predictions on the imminent demise of exponential complexity growth have been a continuous feature of Moore’s Law’s history). The plot’s greatest critic in the late 1960s and the first half of the 1970s was Robert Keyes, a physicist working at IBM’s research laboratory. Keyes published several articles in IEEE Spectrum and the Proceedings of the IEEE in which he contended that the evolution toward smaller and smaller dimensions would soon encounter physical limitations. Keyes argued that the smaller the transistors would become, the higher the dissipated power would be, and the more likely it was that the die would melt. Other limits to miniaturization, Keyes asserted, were electrical resistance, dielectric breakdown, and electromigration, the phenomenon whereby electrical currents carried aluminum atoms with them, thereby breaking the aluminum lines interconnecting transistors. These articles were influential. They garnered its author the W. R. G. Baker prize of the IEEE and a membership in the National Academy of Engineering in 1976. It was essential for Moore and his colleagues to counter the arguments of Keyes and other experts regarding the end of exponential growth in chip complexity. They had to convince the semiconductor community that the plot was valid, because their ability to follow Moore’s plot depended upon the work of engineers developing new materials, processes, and manufacturing equipment outside of Intel.Footnote ²³

But Intel’s managers had other reasons for promoting Moore’s plot. They relied on the plot to sell their own products. They were aware that Intel’s microprocessors were often subpar in comparison with those of competitors such as Zilog and Motorola. “Usually, we did not have the best processor,” House later admitted, “so I was selling futures and Moore’s [plot] was a great way to talk about the future.”Footnote ²⁴ In essence, House told potential buyers that purchasing Intel microprocessors, however imperfect they may be, was buying into an architecture that would become more and more powerful over time as chip complexity increased. This sales pitch, which had no equivalent at Zilog, resonated well with computer, automotive, and telecommunications customers, who were interested in continuously upgrading their products with more powerful microchips and, at the same time, sought to preserve their software investments. House was not alone in using Moore’s plot to sell Intel’s chips. Moore, Noyce, and Grove also employed it in their presentations to customers. The plot remained a major sales tool at Intel well into the 2000s. Talking about Moore’s plot at professional meetings was also a way for Moore and his managers to stimulate the thinking of the user community regarding potential uses for increasingly complex microchips, get a sense of what the users might need, and therefore identify the types of circuits Intel’s engineers should design.Footnote ²⁵

As a result of these promotional efforts, Moore’s plot became increasingly accepted in the American semiconductor community in the late 1970s. Reinforcing its credibility was the fact that it was based, by then, on a greater number of data points. Intel’s commercial success and the growing prominence of its creator also contributed to the plot’s growing acceptance. For much of the 1970s, Intel stood out as the fastest-growing and most-profitable corporation in the entire U.S. microelectronics industry. Moore was increasingly visible as well. Replacing Noyce, he became Intel’s chief executive officer in 1975.Footnote ²⁶ It was within this context that Moore’s plot, in its 1975 version, became referred to as “Moore’s Law.”Footnote ²⁷ The term appeared for the first time in print in an article on the past and future of integrated circuits published by Lester Hogan, Fairchild’s associate chairman, in March 1977. A few months later, the expression was used by Noyce in an article on microelectronics in Scientific American. In the following years, Moore’s Law increasingly showed up in the trade press, in journals of the IEEE, and at technology conferences such as the International Solid-State Circuits Conference (ISSCC). With this semantic shift, the perceived nature of the plot changed. It gained all the authority of a “law.” For many American engineers, Moore’s graph became a near-physical law governing the development of semiconductor technology.Footnote ²⁸

But the universal acceptance of Moore’s Law does not mean that it was adopted as a technology-planning tool by all American microelectronics firms in the late 1970s and early 1980s. In fact, relatively few were the corporations that considered it to be an essential component of their competitiveness and utilized it to guide the development of new technologies. Besides Intel and Fairchild, they consisted mostly of TI, AMD, Motorola, and AT&T (the firm had finally converted to Moore’s Law). At other corporations, Moore’s Law was viewed as a reassurance that the trend toward greater complexity would continue in the foreseeable future. Signetics, a large Silicon Valley–based manufacturer of logic and linear circuits, is a case in point. In the late 1970s and early 1980s, Signetics conducted several planning exercises that argued that Moore’s Law was a long-term trend and there were no immediate physical limitations to the fabrication of finer and finer structures. However, this discussion did not lead the authors of the reports to define a series of technological objectives on the basis of Moore’s curve. They focused exclusively on the next generation of process technology and took competitive pressures, rather than the law’s cadence, as their main goal setter. This utilization of Moore’s Law seems to have been common in most U.S. semiconductor firms at the time.Footnote ²⁹

Revising Moore’s Law and Transforming the Modalities of Its Use

In the early and mid-1980s, Moore and his associates at Intel modified the cadence of Moore’s Law. They also changed the ways in which they employed it for technology planning. These transformations were made in response to fierce competition coming from Japan. Starting in the mid-1970s, Japanese chipmakers emerged as major players in the semiconductor business. They controlled a growing share of the world market for semiconductors. They also became increasingly competent technically and moved up very quickly within Moore’s band. They introduced increasingly complex memories to the market. By 1983 and 1984, they were on par with or ahead of Intel and other U.S. firms for key metrics such as transistor count, transistor size, and the width of metal lines.Footnote ³⁰

The Japanese surge was not predicated on Moore’s Law but on the use of another planning tool, the rule whereby the capacity of memory chips increased by a factor of four every three years. Technical leaders in Japan, such as Yasuo Tarui of MITI’s VLSI program and engineering managers at NEC, Hitachi, Toshiba, and Fujitsu, were well aware of Moore’s Law. However, like their counterparts at most American firms, they viewed it as a reassurance that the complexity and density of integrated circuits would continue to increase. For product and process planning, they preferred another tool, the rule whereby the capacity of semiconductor memories quadrupled every three years. Unlike Moore’s Law, which emphasized transistor counts, the Japanese metric was based on product performance. It also had a different tempo—three years, instead of the two years of Moore’s Law in its 1975 version.Footnote ³¹

Japanese executives employed their rule in ways that were different from Moore’s own utilization of Moore’s Law. They were much stricter in applying it to the development of new products and manufacturing processes. Their engineering groups followed the capacity rule in a highly disciplined and regimented fashion. The focus was on quadrupling product capacity precisely every three years. In contrast, Moore and executives at Motorola and Texas Instruments applied Moore’s Law much more loosely. To outdo Japanese corporations, they emphasized radical process innovation, rather than incremental improvements and strict observance of Moore’s Law. These efforts to leapfrog the Japanese ended in failure and, starting in the early 1980s, Intel and most other American firms commercialized memories with similar capacities significantly later than their Japanese rivals.Footnote ³²

The Japanese surge in integrated circuit complexity forced Moore to increase the cadence of his law. Starting in 1983, he instructed Intel’s engineers to “accelerate [the] rate of technical change.”Footnote ³³ Translating the Japanese capacity metric into component counts, he asked them to increase device complexity at the “rate of four times every three years.”Footnote ³⁴ (figure 2) This became the new formulation of Moore’s Law at Intel. To double the number of transistors per chip every eighteen months, Moore and his managers made very significant investments in process engineering. Substantial resources were devoted to the development of one micron and submicron processes (each process being named after the size of the transistor gate).Footnote ³⁵

Figure 2 Moore’s Law, 1983. Moore defined Moore's Law publicly for the first time as the quadrupling of the number of transistors every three years at the Dataquest Semiconductor Industry Conference in 1983. He also noted that chip design productivity doubled every three years. Source: Gordon Moore, “The VLSI Complexity Crisis,” October 1983. Courtesy of Department of Special Collections, Stanford University Libraries.Footnote ³⁶

Following the Japanese model of disciplined implementation, Moore applied Moore’s Law much more strictly to the engineering of Intel’s products and processes. To stay as close as possible to the new version of the curve, Moore, Vadasz, and other Intel managers coupled Moore’s Law with other planning tools. In the early 1980s, they developed plans for “strategic capability segments” that set technology directions and identified long-range requirements. They later adopted a new managerial instrument that had been pioneered at Motorola in the mid- to late 1970s: the technology roadmap. The technology roadmap defined detailed technical milestones over the next five to ten years. It rested on the expertise of the firm’s engineers and, as a result, obtained their buy-in. It also served as a communication tool across the corporation and with outside suppliers. In 1985, Moore convened a workshop to create such a roadmap at Intel. His marching orders were clear: define “the key research and development activities which we should be involved in to ensure leadership in the areas where we participate” and develop “the technical strategy Intel should pursue.”Footnote ³⁷ He expected “the resulting ‘technology roadmap’” to “form the basis for implementation of basic research activities” up until 1995. In the following years, Intel’s staff regularly updated the roadmap to take new technical and competitive developments into account.Footnote ³⁸

But following Moore’s Law much more strictly also meant developing technologies characterized by different degrees of resolution in parallel and introducing the resulting products sequentially to the market. Intel’s managers called this strategy “pipelining.” “It took on average three years and nine months to design a new processor,” House later reminisced. “If I start development every two years and stagger it, I can stepwise approximate Moore’s Law. But if I wait, if I do only one generation [at a time], I get a four-year step before I get back to Moore’s Law and I am always below it.”Footnote ³⁹ To stay on Moore’s Law, Intel’s engineers introduced a new microprocessor in production every two years, “shrunk” this design (that is, reduced its dimensions through process improvements) each intervening year, and repeated this sequence for the next microprocessor over the following two years. The pipelining of process development and microprocessor design, along with the building of detailed roadmaps, enabled Intel to follow Moore’s curve, in its 1983 version, much more precisely. It also allowed the firm to progressively regain its former position at the top of Moore’s band in the late 1980s and early 1990s. Along with the sole sourcing of its chips and the revival of its manufacturing operations, the relentless pursuit of Moore’s Law enabled Intel to create a near-monopoly for its microprocessors in the fast-growing personal computer market. By 1992, Intel had become the largest semiconductor firm in the world.Footnote ⁴⁰

To respond to the Japanese challenge, Moore and Noyce also built collaborative research organizations with their counterparts at other large chip-making corporations: IBM, Motorola, National Semiconductor, and Texas Instruments. In 1987 they established Sematech, a research consortium aimed at closing the gap in manufacturing with Japanese chipmakers. Because all the corporations dominating Sematech had by then incorporated road mapping into their technology-planning exercises, the drafting and implementation of technology roadmaps became a central activity of the new organization. Indeed, Sematech was launched through the convening of workshops that defined roadmaps for key manufacturing processes such as epitaxy, photolithography, and ion implantation. These roadmaps then provided the basis for the organization’s five-year plan and oriented its research and development activities. Through their involvement with Sematech and a related organization, the Semiconductor Research Corporation (SRC) that financed semiconductor research at universities, Intel’s engineers and managers gained significant experience with collective technology road mapping. They also learned how to articulate Intel’s internal roadmap with the collective roadmaps of Sematech and the SRC.Footnote ⁴¹

Institutionalizing Moore’s Law

Moore further institutionalized Moore’s Law by establishing the National Technology Roadmap for Semiconductors (NTRS) in 1992. The new organization emerged at the convergence point of several developments. The Semiconductor Industry Association (SIA) that represented American microelectronics corporations was interested in reinforcing the technological base and competitiveness of U.S. semiconductor firms. To do so, in early 1991 the SIA formed a new committee—the technology committee—the objective of which was to shape the nation’s semiconductor technology policy, and it gave its headship to Moore. By then, Moore was Intel’s chairman of the board and the most respected figure in the U.S. semiconductor industry. This new policy interest on the part of Moore and the SIA coincided with a retreat of the federal government from technology policy, a trend that emerged at the end of the George H. W. Bush administration and was amplified under Bill Clinton.Footnote ⁴²

Another factor in the formation of the NTRS was the upcoming dissolution of the National Advisory Committee for Semiconductors (NACS). This committee, directed by Ian Ross of AT&T, had been established by Congress in 1988 to develop a national strategy in microelectronics. In April 1991, the NACS sponsored the development of a technology roadmap, MicroTech 2000. This roadmap, elaborated by ninety experts coming from academia, government, and industry, laid out the steps that the semiconductor industry would need to take in order to be one process generation ahead of the Japanese by 2000. This was a very ambitious goal that would require a large increase in the resources allocated to semiconductor innovation and much tighter collaboration among American microelectronics corporations. As the NACS was about to submit its final report to Congress, Ross approached the SIA and asked it to take over the MicroTech roadmap and transform it into a living document that would be regularly updated and managed by a permanent organization.Footnote ⁴³

Moore seized this offer. He saw it as a way of sustaining exponential growth in chip complexity at a time when engineers encountered more and more problems in following Moore’s Law. It was also, for him, an opportunity to reinforce Intel’s and the U.S. semiconductor industry’s competitive position and market share on the global scale, at the expense of the Japanese. However, judging the tempo of the NACS roadmap and the closeness of the collaborations it required to be impractical, Moore set out to reshape it. He was interested in creating a national roadmap that would take over the roadmap of the NACS and those of Sematech and the Semiconductor Research Corporation, two organizations controlled by the SIA. Using Moore’s Law as its primary guidance, the new roadmap would provide long-range technology planning to the industry as a whole. In particular, it would identify “holes” requiring additional research efforts and focus the activities of SRC and Sematech and the investments of the federal government on filling these holes. On the model of Intel’s internal roadmaps, the national roadmap would also deliver “actionable” planning. It would be realistic enough for corporations and governmental organizations to focus on reaching its main milestones.Footnote ⁴⁴

In the fall of 1991, Moore convinced the CEOs of other large microelectronics corporations to back this project. There was much in it that they liked. Taking advantage of the relaxation of antitrust laws since the mid-1980s, Moore proposed to them, in essence, that they form an innovation cartel. This cartel would set the direction and pace of innovation for the industry as a whole. It would be dominated by large corporations through their representation in key committees. With its focus on sustaining exponential complexity growth, it would also set rules for competition that favored the most established corporations because of their greater engineering and financial resources. In addition, Moore gained support for the national roadmap from members of the NACS and several branches of the federal government, including the Department of Defense and the Office of Science and Technology Policy.Footnote ⁴⁵

At Moore’s request, William Howard, a former Motorola executive, and Robert Burger, the head of the SRC, organized the workshop that defined the SIA’s national roadmap in November 1992. Howard, Burger, and executives from Intel, IBM, AT&T, Motorola, Hewlett-Packard, and Texas Instruments, specified the roadmap’s complexity metrics, the milestones in terms of gate counts, bit tallies, and clock frequencies, for five process generations over the next fifteen years. Howard and Burger also invited 170 experts from a wide variety of firms and, to a lesser degree, from academia and governmental organizations, to populate the working groups that translated these metrics into detailed lists of development needs for lithography, interconnects, packaging, and other technologies.Footnote ⁴⁶

Indicative of the general thrust of the workshop, the removal of obstacles to exponential complexity growth, was Moore’s introductory keynote speech (figure 3). After stressing the critical importance of the roadmap for national competitiveness, Moore asked attendees to share their “BEST knowledge and thinking” on “what will happen if we CONTINUE [the exponential trend in chip complexity], where that will put us competitively, and what LONGER RANGE activities should be undertaken either to lay a foundation [for technologies needed to stay on Moore’s Law], or to assure that a possible alternative is not precluded.… Our task is to remove roadblocks to continue the trends [toward greater integration] as long as we can and anticipate where we hit the stops.”Footnote ⁴⁷

Figure 3 Setting the objective for the NTRS, 1992. In his keynote speech at the SIA road-mapping workshop, Moore focused attendees' attention on exponential complexity growth over the next fifteen years, the crossed-out area in the graph. Source: Gordon Moore, "Moving to a Single Roadmap," November 17, 1992. Courtesy of Department of Special Collections, Stanford University Libraries.Footnote ⁴⁸

The roadmap that ensued was published by the SIA in early 1993. It was highly influential. So was the update report that followed in 1994. These documents were employed throughout industry and government to prioritize investments regarding the development of microelectronics technologies. At Moore’s urging, Sematech and the SRC realigned their programs to address the issues highlighted by the roadmap. For example, the SRC required that all research proposals it received from academic investigators emphasize their relevance to the roadmap. As Moore had hoped, the NTRS also influenced governmental action. The Defense Advanced Research Projects Agency, the National Science Foundation, and other federal agencies awarded hundreds of millions of dollars in grants for semiconductor research to universities in strict accordance with the roadmap. Faculty members requesting support for semiconductor projects laying outside of the roadmap had very little chance of getting funded. Responding to significant pressure coming from the Clinton administration, the national laboratories expanded their research programs on semiconductors. They collaborated closely with Intel and other corporations, especially in the area of EUV lithography, which promised to pattern nanoscale microchips.Footnote ⁴⁹

Microchip makers also employed the technology roadmaps internally to allocate resources and coordinate R&D efforts with other firms, but the greatest users of the NTRS reports were the suppliers of specialized materials and manufacturing tools. Indeed, one of the primary functions of the roadmap was to communicate the specific needs of integrated circuit manufacturers to the producers of electronic chemicals and production equipment. These suppliers devised their own product offerings to meet the roadmap’s requirements. In short, the NTRS became nearly sacrosanct across the U.S. microelectronics community. Moore was one of the very few individuals who could publicly find fault with the roadmap and its tempo. In the early andmid-1990s, he did so repeatedly to prevent blind observance of the roadmap and to attract the attention of the semiconductor community on the economic and technological obstacles facing the industry in its effort to follow Moore’s Law. As a result of Moore’s public pronouncements, the 1994 roadmap gave greater attention to economic constraints than its prior version.”Footnote ⁵⁰

The near universal embrace of the roadmap had major repercussions. Microelectronics corporations that had, until then, focused on the next generation of process technology started to engage in long-range planning. They all adopted Moore’s Law as their primary technology planning tool. Moore’s Law became the norm. The NTRS also drove technological convergence. It led to the standardization of materials, equipment, and manufacturing processes across the whole industry. “The roadmap steers competitors toward nearly identical memory and microprocessor technologies,” a Hewlett-Packard manager closely involved with the roadmap remarked in 1995. “This convergence is critical. It enables equipment suppliers to develop tools with cost effective performances since all customers must basically use them in the same way.”Footnote ⁵¹

The pace of technology development also increased significantly. In 1995, Intel, Texas Instruments, and other leading firms publicly announced that process technologies progressed more rapidly than the objectives set by the roadmap. This acceleration was made possible by the greater focus, efficiency, and urgency, and the increased resources the NTRS brought to semiconductor research, but it can also be explained by a simple social phenomenon. Because all corporations knew what the targets were, they went faster than the pace set by the roadmap in order to gain an advantage over their competitors. By establishing Moore’s Law at the very center of the industry, Moore had changed the very slope of Moore’s band, tilting it upward.Footnote ⁵²

Competing with Moore’s Law and the Roadmaps

To stay at the leading edge, Moore and his closest associates, Grove and Barrett, positioned Intel’s internal technology roadmap ahead of the NTRS in the early and mid-1990s. Intel’s roadmap was at least a year ahead of the national roadmap. It also differentiated itself from it, by selectively emphasizing areas in which Intel could gain a technological advantage. Also critical for Intel maintaining its leading position in Moore’s band were the close relations it forged with equipment suppliers. The chipmaker invested heavily in U.S. equipment manufacturers, such as Silicon Valley Group Lithography that fabricated advanced production tools. It also put significant engineering time in the development, improvement, and testing of their equipment, but these investment of time and money came with the condition that Intel would be the first to purchase the tools and employ them on its own manufacturing lines. Along with the timing of the internal roadmap, close relations with suppliers enabled Intel to produce the most complex microchips. Its grip over the semiconductor market increased.Footnote ⁵³

Later in the decade, Intel’s management took control of the NTRS to reinforce their firm’s technological and competitive position over the long term. Critical for this takeover was Paolo Gargini, an engineering manager close to Barrett. Like Moore, Barrett was increasingly concerned that the NTRS was not detailed and quantitative enough. In his view, it also did not concentrate sufficiently on the long range, especially the significant obstacles Intel and other firms would need to overcome in order to produce microchips with nanoscale features. For instance, no one knew how to pattern microchips at the 100-nanometer process node and those that would follow. Materials that had been critical for the fabrication of integrated circuits since the 1960s would cease to function properly. Layers of polysilicon and silicon oxide would become so thin that electrons would move through them. Entirely new materials would have to be developed for nanoscale integrated circuits.Footnote ⁵⁴

Exploiting inconsistencies in the 1994 roadmap and benefitting from the considerable heft of his employer, Gargini took control of the NTRS, thereby transforming the innovation cartel into a quasi extension of Intel. He became vice-chair of the 1997 roadmap and the head of its most important committee, the one setting the roadmap’s principal targets. Gargini chaired the next iteration of the roadmap and those that followed over the next fifteen years. This position of power enabled him and Barrett to set the pace for technology development for the entire American and, later, global microelectronics industries. Taking stock of the acceleration in the development of manufacturing processes since 1994, Gargini stipulated in the 1997 roadmap that the industry would introduce new process generations every two years, instead of every three years, for the next six years. He knew well that this choice would further accelerate complexity growth, as the largest and most technically proficient firms would go faster than the roadmap and introduce new manufacturing processes in less than two years. In contrast, the smaller corporations or those that were already behind in Moore’s band would struggle to keep pace. They would also have to buy increasingly expensive manufacturing equipment at a time when their returns on investment, because of their lateness, would most likely decrease. Gargini and Barrett surmised that many would abandon the complexity race over the medium term.Footnote ⁵⁵

To focus the attention of the U.S. semiconductor community on the long-range problems facing Moore’s Law, Gargini transformed the format of the NTRS. Under his leadership, the roadmap’s main targets were stipulated in much greater detail, including not only transistor counts, but also chip size, performance, defect density, power dissipation, and manufacturing cost. The main change, however, was in the tables produced by the working groups. These tables converted the overall roadmap targets into a set of objectives for the many technologies involved in the design and processing of microchips. They became much more detailed. They were also color coded: yellow indicating the targets for which new technologies were then in development and red for those no expert knew how to reach. This color scheme concentrated the attention of researchers at firms, universities, and national laboratories on the “red” problems, the pressing questions confronting Intel and the industry as a whole.Footnote ⁵⁶

One of the most significant issues was the development of high K materials that would replace polysilicon in transistor gates. “I had the idea,” Gargini later reminisced, “that by the middle of the next decade, 2004/5/6, we had to introduce high K metal gates. At the end of the [1997 roadmap] meeting, the university people were terrorized [by this prospect]. It was a terror for all of them [that] all of a sudden something that was a very low-key project was becoming very important.… This created a panic.”Footnote ⁵⁷ Artfully prompted and maintained by Gargini, this concern led research groups at American universities to work on new insulating materials for transistor gates. Many other projects were also launched to develop low K materials that would not have the limitations of silicon oxide. Federal agencies financed these research programs.Footnote ⁵⁸

However, it rapidly became clear to Barrett and Gargini that the entire financial and engineering resources devoted to semiconductor research and development in the United States would not be sufficient to solve the many problems of nanoscale microchip manufacturing. In order to find cost-effective solutions for Intel, they would need to mobilize the resources of foreign corporations and research establishments as well. This assessment persuaded Gargini to internationalize the roadmap by opening it to the Japanese, Korean, Taiwanese, and European microelectronics industries in 1998. Another reason for creating the International Technology Roadmap for Semiconductors (ITRS) was the efforts in Japan to form a national roadmap that would compete with the NTRS. Japanese corporations had, by then, lost their dominant market share to American chipmakers. They were interested in creating their own roadmap in order to shore up their declining competitiveness. The formation of a Japanese roadmap represented a sizeable threat for Intel. It would convince equipment makers to divert part of their resources toward the development of tools meeting the stipulations of the Japanese roadmap instead of those of the NTRS. Gargini stifled this project by threatening a rekindling of the semiconductor wars of the 1980s. He persuaded the Japanese to join the upcoming ITRS. The European, Korean, and Taiwanese semiconductor industries followed.Footnote ⁵⁹

The international roadmap was closely patterned after the national roadmap. It was also dominated by Gargini and Intel. The ITRS further expanded the use of Moore’s Law as a technology planning tool. As they joined the ITRS, the Japanese embraced Moore’s Law. The international roadmap also led to process convergence at the global scale. Under Intel’s guidance, it piloted the development of new semiconductor technologies in the United States, Japan, Europe, and, to a lesser extent, Taiwan and South Korea for much of the 2000s. The European Union and Japanese and European governments partially financed these research programs. Heavy R&D investments on the global scale and the inner workings of the international roadmap enabled Intel to identify the best solutions to the challenges posed by the shift to the nanometer scale and integrate them into its own manufacturing processes. Intel, for instance, introduced microprocessors with high K metal gates to the market in 2007. It was the first corporation to do so.Footnote ⁶⁰

The ITRS weakened American, Japanese, and European corporations. They were put on Intel’s “treadmill,” struggling to sustain the pace imposed by the chipmaker and solve the considerable problems of producing chips with nanoscale features. Because of their active involvement in the roadmap, Japanese firms lost some of their strategic capability. Intel further undermined their competitive position by setting the ITRS targets significantly behind those of its own internal roadmap. For example, Intel announced its use of low K materials a year and a half ahead of the ITRS official target. As a result of the pace imposed by Intel and the growing cost of manufacturing equipment, more and more microelectronics corporations in Japan, America, and Europe dropped out from exponential scaling in the mid- to late 2000s. This left only a handful of firms actively pursuing Moore’s Law, the most prominent of which were Intel, TSMC, and Samsung.Footnote ⁶¹