I. INTRODUCTION
The demand for gigabit-per-second short-range wireless communication systems is increasing daily while the opening up of the 57–64 GHz unlicensed band presents new opportunities. IEEE standard 802.15.3c [1] defines the specifications for wireless personal area network (WPAN) in a 60 GHz band, which enables applications such as uncompressed video streaming, office desktop data transfer, and kiosk file downloading. IEEE 802.11ad [2] is tasked to amend the existing 802.11 WLAN standard to enable a maximum throughput of at least 1 Gbps, which is comparable to the existing wired LAN products. Furthermore, the wireless gigabit alliance has proposed and launched the technology to drive the industry convergence to a single radio in the unlicensed 60 GHz spectrum [3].
The millimeter-wave (mm-wave) power amplifier (PA) design has been one of the most significant challenges to a full integration of a complete wireless communication system on a single chip in the 60 GHz band. To set up a communication range of 1 m, an output power of 10 dBm is required while a bandwidth of 7 GHz is preferred to cover the whole frequency band and enable channel bonding. Although mm-wave PAs have traditionally been implemented in III–V compound semiconductors such as GaAs and InP, CMOS technologies are now capable of operating at mm-wave frequencies [Reference Doan, Emami, Niknejad and Brodersen4–Reference Boers10]. CMOS technologies can offer the advantages of integration density on a single chip and the potential for reducing cost with increasing production volume. However, the low operation voltage of an MOS transistor, limited by the low breakdown voltage, and lossy passive components restrict the performance of CMOS PAs in 60 GHz band. One potential solution is to use the power combining technique [Reference Reynaert and Niknejad11], which combines the output power of several unit PAs to achieve a higher output power. Increasing the number of unit PAs may improve the output power whereas it complicates the floor plan of the PA. Wilkinson or hybrid power combiners have been utilized that require quarter-wave transmission lines (TLs) and thus consumes relatively large silicon area [Reference Law and Pham12].
This paper presents a 60 GHz wideband PA [Reference He, Li and Reynaert13] using a transformer-based power combining technique to improve the output power and save chip area. It is fabricated in a 65 nm low-power bulk CMOS technology. The paper is organized as follows. Section II addresses the mm-wave PA design strategies and explains the advantages of using differential cascode amplifier topology and power combining technique. Section III details the PA design. Experimental results and conclusions are presented in Sections IV and V, respectively.
II. DESIGN STRATEGIES FOR MM-WAVE PA
At mm-wave frequencies, new challenges are posed on the PA designs. As the operating frequencies approach a fraction of the transistor's cut-off frequency, the decreasing active power gain of the transistor and high-loss passives limit the gain and efficiency of PAs, which increase the system power consumption and potentially cause thermal dissipation issues. Besides, the sizes of components are comparable with wavelength and thus microwave theory applies. Device and interconnect parasitics represent a large portion of the total impedance or admittance at a node, and so the layout optimization and parasitic extraction are crucial. In this section, our treatments will be focused on cascode amplifier stage and power combining technique to improve the output power, and the differential signaling to ensure signal integrity.
A) Cascode amplifier stage
Scaling of CMOS technologies leads to reduced channel length and gate oxide thickness. Although mm-wave circuits benefit from this scaling trend, its direct negative impact on PA design is the lowered breakdown voltage. The breakdown mechanisms of MOS transistors can be categorized as gate oxide breakdown, drain-bulk breakdown, punch-through, and hot carrier degradation while the last one is the limiting factor [Reference Aoki14]. Hot carrier degradation occurs when the carriers in the channel are accelerated by the large drain-to-source voltage. In 40 nm CMOS technology, the maximum DC and RF drain-to-source voltages have to be smaller than 1.25 and 1.4 V, respectively, when the gate bias voltage is 0.7 V, to ensure a 10-year lifetime [Reference Stephens, Vanhoucke and Donkers15]. In the proposed PA, cascode stage is used to extend the output voltage swing. Figure 1 shows the cascode and common-source (CS) stages with output matching network. The voltage waveforms at different nodes of the cascode stage are studied. As shown in Fig. 2, since the drain and source voltages of the transistor M 2 are in phase, the actual voltage across the transistor V ds is reduced by 30%. Compared to the CS stage with the same breakdown voltage, cascode stage has 1.5 dB improvement in output power when the optimum load impedance is adjusted.
Fig. 1. Cascode and CS stages with output matching networks.
Fig. 2. Transient voltage waveforms of the cascode stage (Fig. 1) with a matched output.
Apart from the capability to deliver more output power, the cascode stage alleviates the miller effect and therefore presents wide bandwidth and better stability. The improved reverse isolation also eases the design procedure. Compared with the CS stage, simulation results show that the cascode amplifier has more than 3 dB in maximum power gain (G max), exceeds15 dB in S 12, and is unconditional stable at 60 GHz, as shown in Fig. 3.
Fig. 3. Simulated performance comparison between cascode and CS stages in (a) G max, (b) S 12, and (c) k-factor. The size of the back-annotated transistor is 40 µm with 1 µm finger width.
B) Power combining technique
The power combining technique provides another solution to improve the output power. As discussed in the previous section, the low breakdown voltages limit the voltage swing at PA's output to approximately ±0.5 V for a CS stage and ±0.7 V for a cascode stage, respectively, in 65 nm CMOS. An impedance transformation network is usually inserted between the output stage and the transmit antenna to achieve the required output power. A large transformation ratio and lossy passive components significantly degrade the efficiency of the PA at mm-wave frequencies. Power combining technique combines the output power of several unit PAs, which can achieve relatively high efficiency. When all the unit PAs have the same output impedance, the total output power delivered to the load equals [Reference Reynaert and Niknejad11]
where N is the number of the unit PAs, m the transformer turn ratio, V PA the output voltage swing of the unit PA, and R L the load of the complete PA. It can be seen that the impedance transformation ratio can be traded off with the number of unit PAs. An output matching network with low transformation ration leads to higher efficiency and broader bandwidth [Reference Aoki, Kee, Rutledge and Hajimiri16]. Therefore, a transformer-based power combiner was adopted in this design, as shown in Fig. 4. The power combiner was implemented in an overlay configuration with top two metals, achieving a coupling factor of 0.7. Instead of placing the primary and secondary coils on top of each other, an offset was introduced between the two coils to improve the matching between the load and the output impedance of the PA. The metal width of the two coils was optimized to minimize the insertion loss (1 dB) and extend the self-resonance frequency (100 GHz) of the power combiner.
Fig. 4. Overlay transformer-based power combiner.
C) Differential signaling
To ensure the signal integrity at mm-wave frequencies is another challenge. It is not easy to make a low-impedance ground plane in the mm-wave frequency range. For instance, at 60 GHz, a 10 pH inductance in the ground plane adds 4 Ω reactance to the AC ground of a single-ended amplifier stage. This degeneration inductance reduces power gain and efficiency of the PA and it has to be modeled well. The virtual ground nature of the differential pair provides a local AC ground, which avoids this unwanted effect from the ground inductance, and high-frequency performance can be restored. Although the differential circuit consumes twice as much power as the single-ended circuit, it provides 3 dB extra output power.
For a multistage amplifier, unwanted coupling of signals between stages may cause instability [Reference Cheung and Long17]. One of the primary undesired couplings is through on-chip supply or ground lines. The differential amplifier is not immune to this problem especially when the PA produces highly nonlinear outputs or it is integrated in a system. Illustrated in Fig. 5, the supply line and signal path close the unintended loop that does not affect differential operations. However, common-mode positive feedback can occur between the two gain stages at certain frequency. Similarly, the ground bounce also affects the stability of a multistage amplifier. Therefore, the supplies and grounds of the driver stage and the output stage were separated in the design to improve the stability of the PA. Note that supply and ground separations between stages are only feasible in differential circuits for differential signaling provides a specified signal current return path.
Fig. 5. Two-stage differential PA showing the potential loop for the common-mode instability.
III. CIRCUIT DESIGN
This section details the 60 GHz PA design. The design was implemented in 65 nm bulk CMOS technology with f T/f MAX of 170/230 GHz. The transistor used in the design is biased at 0.2 mA/μm to maximize the power gain. The schematic of the amplifier is shown in Fig. 6. It consists of two unit PAs and each unit PA has a driver stage and an output stage. The pseudo-differential cascode amplifier is used to extend output voltage swing and improve the stability. The common-gate stage is laid out in close proximity to create a virtual ground at the gate and relax the need for decoupling capacitor. Load-pull simulations are performed for both output and driver stages. The optimum load impedances are then determined to maximize the output power. Even for the differential circuit, the inductance in the ground plane is still problematic when the transistor size goes large as every unit transistor sees different local ground. A 10 pH source degeneration inductance implemented with wide metals is applied to mitigate this problem, as shown in Fig. 7. The source degeneration inductor can be well modeled in the output stage and included in the circuit simulations. Although it reduces the power gain of the amplifier, the source degeneration inductor increases the input impedance of the output stage to ease the interstage matching and reduce the insertion loss of the matching network. The inductor is shielded from the signal path by floating metal strips. Compared with the output stage, the driver stage is scaled by a factor of 2.5 in size, which is intended to provide sufficient signal power to drive the output stage.
Fig. 6. Simplified schematic of 60 GHz PA.
Fig. 7. Source degenerated inductor shielded from the signal path by floating metal strips.
For the passives, transformer-based structures are extensively employed in order to reduce the chip area. The transformers are implemented in the top two metals (metals 6 and 7). Both metals have the thickness of 0.9 µm and the coupling factor of the transformer is around 0.7, as mentioned in Section II. The input power divider matches the input impedance of the PA to 50 Ω input and provides two pairs of differential signals to the driver stage while the output power combiner sums the power from two unit PAs and transform the 50 Ω load to the optimum load impedance for each PA. A coupling transformer and a slow-wave differential TL [Reference Cheung and Long18] are employed for interstage matching network. The adoption of the differential TLs simplifies the transformer design. The turn ratio of the transformer is 1:1 and high-power transfer efficiency can then be expected. The floating metal strips are placed beneath the TLs to shield the signal lines from the lossy substrate. The supply and bias lines can also be easily routed under the floating strips without affecting the RF performance. The supply and ground lines of the driver stage and output stage are separated from each other to ensure the stability. The low-Q decoupling capacitors are used for the supply lines to avoid any potential common-mode oscillations.
IV. EXPERIMENTAL RESULTS
The microphotograph of the PA testchip is shown in Fig. 8 with the PA core area of only 0.3 mm2. The 60 GHz PA was measured via on-wafer probing. Two Model 67A Picoprobe GS/SG Probes were used for the input/output probing. Small signal S-parameter measurements were performed with a 67 GHz Agilent E8361C vector network analyzer. A short-open-load-through calibration method was applied using a separate calibration substrate. The large signal characterization was carried out with a 110 GHz Agilent power meter. The PA consumed 143 mA from a 1.6 V supply voltage at DC.
Fig. 8. Microphotograph of the PA testchip.
Figure 9 shows small-signal s-parameter results of the PA. The PA has a peak small-signal gain S 21 of 10.2 dB at 58 GHz. The 3-dB bandwidth is around 12 GHz (50–62 GHz). The reverse isolation is better than 33 dB within the measurement frequency range (25–65 GHz). The PA achieves broadband output matching (S 22 < −10 dB) across the entire working frequencies. S 11 is better than −6.5 dB. Note that the input matching of PA is not as important as the output matching since the PA will be connected to an on-chip up-converter in the transmitter.
Fig. 9. Measured s-parameter of the PA versus frequency.
Figure 10 illustrates the large signal behavior of the PA at 58 GHz. By increasing the input power, the PA shows an output saturation power (P SAT) of 14 dBm and output 1-dB compression point (P O1 dB) of 10.8 dBm. The peak power-added efficiency (PAE) and drain efficiency (DE) are 7.2 and 14.8%, respectively, as shown in Fig. 11. Figure 12 shows the output power variations over the frequency band. A flat P O1 dB has been observed between 52 and 60 GHz and the variation is smaller than 1.5 dB. The P SAT is between 12 and 14 dBm from 52 to 61 GHz.
Fig. 10. Measured gain and output power of the PA versus input power at 58 GHz.
Fig. 11. Measured DE and PAE of the PA versus input power at 58 GHz.
Fig. 12. Measured P O1 dB and P SAT of the PA versus frequency.
The performance of the PA has also been studied by varying the supply voltage of the driver stage. As shown in Fig. 13, when the supply voltage of the driver stage is swept from 1 to 2.2 V, P O1 dB increases from 7 to 11.8 dBm and P SAT from 9.7 to 14.8 dBm. Similar results were not observed when the supply voltage of the output stage was increased. This indicates that the driver stage is a bit under-designed and output power compression point is limited by the driver stage. It can probably be attributed to the process variations or the inaccurate modeling of the transistor. Better performance can be expected if the high-frequency transistor model is corrected or the size of the driver stage is increased so that enough power can be delivered to the output stage.
Fig. 13. Measured P O1 dB, P SAT and gain of the PA versus the supply voltage of the drain stage at 58 GHz.
Table 1 compares the performance of this PA with recent published 60 GHz CMOS PAs. These amplifiers employ either CS or cascode topologies. Most designs use a differential (Diff.) configuration due to its advantages over the single-ended (Sing.) circuit at mm-wave frequencies. This work, [Reference Chowdhury, Reynaert and Niknejad6, Reference Chan, Long, Spirito and Pekarik7, Reference Boers10], uses transformers for the matching networks to permit compact layouts. Power combining (PC) techniques are exploited in this work and [Reference Law and Pham9] to achieve saturated output powers of 14.8 and 19.9 dBm, respectively. However, [Reference Law and Pham9] uses four-way Wilkinson power combiners and thus consumes relatively large chip area. From this comparison, it can also be noticed that the PA implemented in CMOS-SOI [Reference Siligaris8] stands out with the highest PAE as the losses of the passives are smaller.
Table 1. 60 GHz CMOS power amplifiers' performance comparison.
*2.2 V supply voltage is applied to the driver stage.
†Core area of the PA is calculated based on the dimensions of the chip.
V. CONCLUSION
A 60 GHz PA was designed using 65 nm bulk CMOS technology. To overcome the low breakdown voltage of the transistor in nanometer CMOS technology, the power combining technique and cascode amplifier were used to maximize the output power. Cascode topology can also improve the reserve isolation and ensure the stability. Differential signaling was employed to mitigate the parasitic inductance in the ground plane and allow the ground separation between the driver stage and output stage. Transformer-based passives were extensively employed in the design to realize high-efficiency matching networks and permitted a compact layout. The PA prototype achieves a small signal gain of 10.2 dB with a 3 dB bandwidth of 9 GHz. The maximum saturated output power is 14.8 dBm with a peak PAE of 7.2%. The reverse isolation is better than −33 dB across the working frequencies.
ACKNOWLEDGEMENTS
This work is supported by ST-Ericsson Zaventem, IWT, and PANAMA project. The authors would like to thank ESAT-Telemic and Rohde and Schwarz for their support with the measurements.
Dixian Zhao received a B.Sc. degree in microelectronics from Fudan University, Shanghai, China, in 2006, and an M.Sc. degree in microelectronics from Delft University of Technology, the Netherlands, in 2009. Currently, he is working toward a Ph.D. degree at Katholieke Universiteit Leuven, Belgium. From late 2005 to 2007, he was with Auto-ID Lab, China, designing the non-volatile memory for passive RFID tags. From 2008 to 2009, he was an intern at Philips Research, Eindhoven, where he designed a 60 GHz beamforming transmitter for presence detection radar. From 2009 to 2010, he was with TU Delft where he developed the 94 GHz wideband receiver for imaging radar. His current research interests include RF and millimeter-wave integrated circuit design for wireless communications.
Ying He obtained her master degree of electrical engineering in K.U.Leuven in 2011. She worked in ESAT-MICAS of K.U.Leuven as a research assistant. In 2009, she accomplished the internship in ST-Microelectronics (Today ST Erricson). She designed and measured the 60 GHz power amplifier with power combiner.
Lianming Li was born in Runan, Henan province, China, in 1978. He received his bachelor degree in physics and master degree in electrical engineering in Southeast University, Nanjing, China, in July 2001 and April 2004, respectively. During his master study, he worked in high-speed circuits design in Institute of RF-&OE-ICs, the Department of Radio Engineering, Southeast University, Nanjing, China. From September 2006 on, he is a research assistant of ESAT-MICAS, Katholieke Universiteit Leuven, Belgium, working toward the Ph.D. degree. His present research interests focus on millimeter-wave circuits design and the phase-lock loop circuits design.
Dieter Joos received the master industrial science degree from De Nayer Institute, in 1999. During 1998–1999 he did an internship with Alcatel Space division, where he developed and evaluated an ALC circuit for on-board commercial satellite communication equipment. In 1999, he joined Alcatel microelectronics, where he worked as an analog design engineer on first-generation cmos BlueTooth and 802.11 g. In 2002, Alcatel(AME) became part of ST Microelectronics, where he developed next-generation BT(EDR). In ST Microelectronics(today STericsson), he has been leading the receiver developments for multiple generations of connectivity. Every receiver solution has been managed from the research phase until the productions phase.
Wim Philibert (born 1971 in Antwerp, Belgium) obtained his master degree in electrical engineering in 1995 from KUL, the Catholic University of Leuven, Belgium. Wim worked as a development engineer for Thales Alenia Space (formerly Alcatel Space Industries) where he designed and tested microwave and RF-frontend components for commercial satellite communication equipment in L-, C-, Ku-, and Ka-band. Typical end products included indoor and outdoor frequency converters, transceivers, and power boosters. He has developed PCBs and hybrid circuits for RF oscillators, PLLs, filters, mixers, and also designed several MMICs (Microwave Monolithic IC) for low-noise amplification and vector modulation. In 2007, Wim joined the Connectivity division of ST-Microelectronics (now ST-Ericsson) where he designs analog and RF CMOS ICs for applications such as Bluetooth, FM, GPS, and NFC.
Patrick Reynaert received his M.Sc and Ph.D. degrees from the Katholieke Universiteit Leuven, Belgium, in 2001 and 2006, respectively. During 2006–2007, he was a post-doctoral researcher at UC Berkeley and a member of the Berkeley Wireless Research Center, where he worked on mm-wave CMOS circuits. For this research, he received a fellowship of the Belgian American Educational Foundation (B.A.E.F.). During the summer of 2007, he was a visiting researcher at Infineon Technologies, Austria, Villach, where he worked on base station power amplifiers. Since October 2007, he has been an associate professor at the Katholieke Universiteit Leuven, Department of Electrical Engineering ESAT-MICAS, and is leading the research on RF power amplifiers and CMOS mm-wave circuits.
