Introduction
Slow-wave transmission lines (SWTL) are promising building blocks for mm-wave integrated circuit (IC) designs in CMOS due to the high achievable transmission line Q-factors [Reference Cheung and Long1, Reference Franc, Pistono, Meunier, Gloria and Ferrari2]. For a required electrical length, a higher transmission line Q-factor results in lower loss, leading to more efficient circuits like couplers, filters and power dividers. The most common SWTLs investigated in literature are the slow-wave coplanar waveguide (S-CPW) [Reference Cheung and Long1–Reference Kaddour, Issa, Franc, Corrao, Pistono, Podevin, Fournier, Duchamp and Ferrari4] and a transmission medium designated by prior literature as slow-wave microstrip (S-MS) [Reference Amin, Wang and Li5, Reference Lee and Park6]. The operating principles have been described in detail in prior literature [Reference Franc, Pistono, Meunier, Gloria and Ferrari2, Reference Kaddour, Issa, Franc, Corrao, Pistono, Podevin, Fournier, Duchamp and Ferrari4, Reference Amin, Wang and Li5], with some recent examples in literature [Reference Kim and Nguyen7–Reference Sharma, Saadi, Margalef-Rovira, Pistono, Barragan, Lisboa de Souza, Ferrari and Bourdel14] clearly illustrating its value in mm-wave CMOS circuit design.
S-CPW has been the topic of extensive parametric study for transmission line slow-wave factor and Q-factor [Reference Cheung and Long1, Reference Horestani, Al-Sarawi and Abbott15], as well as equivalent circuit modelling [Reference Bautista, Franc and Ferrari3]. There has, however, not been a systematic comparison of S-CPW and S-MS in terms of (i) propagation mode, and (ii) Q-factor for comparable characteristic impedance (Z 0). Some studies have been carried out on the effect of Z 0 on Q-factor in slow-wave CPS (S-CPS) [Reference Horestani, Al-Sarawi and Abbott15], but they did not elaborate on the methods or process geometry, and, to the best of the authors' knowledge, no measurement verification has been shown.
This paper presents the first comparative study on the propagating modes and effect of Z 0 on Q-factor for S-CPW and S-MS. The data presented here may be used to select Z 0 values for S-CPW and S-MS line components in CMOS circuits that maximise transmission line Q-factors. This may be valuable to the application of S-MS and S-CPW in designs where there is a need for low-loss transmission line sections, but freedom in the selection of Z 0. Examples include impedance matching networks [Reference Parveg, Varonen, Karaca, Vahdati, Kantanen and Halonen9], transmission zeros for filters [Reference Franc, Pistono, Gloria and Ferrari16], or tank resonators for mm-wave VCOs [Reference Sharma, Saadi, Margalef-Rovira, Pistono, Barragan, Lisboa de Souza, Ferrari and Bourdel14]. It also shows that these two types of SWTL are very similar in terms of propagation mode, despite the differentiating nomenclature established in literature. The analysis setup and transmission line geometries are discussed in Section II, followed by the simulation setup and measurement validation in Section III. The analysis of the mode propagation is carried out in Section IV. Results of the effect of Z 0 on the Q-factor are shown and discussed in Section V, and the paper concludes in Section VI.
Analysis setup
Parameter extraction
The symmetric transmission line ABCD parameters can be calculated from S-parameters, from which the parameters α, β, ɛ r(eff), γ, Q and Z 0 can be extracted using [Reference Lourandakis, Nikellis, Tsiampas, Yamaura and Watanabe12, Reference Vecchi, Repossi, Eyssa, Arcioni and Svelto17]:
where γ is the complex propagation constant, l the length (mm), Z 0 the characteristic impedance (Ω), α the attenuation constant (dB/mm), β the phase constant (degrees/mm), Q the quality factor, and ɛ r(eff) the effective relative permittivity.
Simulations were performed using the HFSS 3D FEM solver with the gap port inductance de-embedded [18]. The transmission lines were implemented in the AMS C35 process with four metal layers and thick M4 (≈3 μm) option. All the simulated transmission lines have a length of 300 μm, which results from a compromise between the precision of the extracted attenuation constant (dB/m), and the inaccuracies in extracting characteristic impedance at frequencies where the line length approaches λ/2 electrical length (due to standing-wave effects).
Transmission line geometries
The slow-wave transmission lines under consideration are shown in Fig. 1. The CPW and S-CPW strips are implemented on the top metal layer (M4), with S-CPW using M3 for the shielding strip patterning (Fig. 1(a)). The microstrip uses M4 for the signal conductor and M2 for the ground plane, while the S-MS [Reference Amin, Wang and Li5] uses M4 for the signal conductor, M3 for the shielding strip layer, and M2 for the slotted ground plane (Fig. 1(b)). This ensures similar separation between the shielding strips and the signal conductor in both S-CPW and S-MS lines, leading to comparable Z 0 ranges. The gap in the S-MS ground plane increases the linear inductance as compared to classical microstrip line, without changing the linear capacitance (resulting in a slow-wave behaviour), at the cost of increased chip area. By the same way, for the S-CPW, the shielding strip patterning leads to an increase of the linear capacitance, as compared to classical CPW without changing the linear inductance (resulting in a slow-wave behaviour), here again at the cost of increased chip area. This increase in inductance for S-MS lines and capacitance for S-CPWs may suggest that the propagation modes are different, but this is simply due to the reference taken for the linear inductance or capacitance increase, either microstrip or CPW. As already specified above, we show in section III that the two modes are in fact similar.
Fig. 1. Cross-sectional views of the slow-wave transmission line structures. (a) S-CPW (b) S-MS.
Measurement validation of simulation setup and extraction method
To validate the simulation approach, the S-CPWs from [Reference Cheung and Long1, Reference Franc, Pistono and Ferrari19] were simulated and compared to measurement results, extracting the transmission line parameters as described in Section II. Prototypes were characterized on an Anritsu VNA with GSG wafer probing, with the effects of probe pads de-embedded using the technique in [Reference Mangan, Voinigescu, Yang and Tazlauanu20]. The resulting comparison for S-CPW1 is shown up to 110 GHz in Fig. 2. The results at 60 GHz, for all four S-CPW geometries, are summarized in Table 1, and compare extremely well with the parameters extracted in [Reference Cheung and Long1, Reference Franc, Pistono and Ferrari19]. A maximum error of below 5% for ɛ r(eff) and below 16% for α is obtained in all cases, which are comparable to the measurement error. An increased error in α is evident above 70 GHz (also observed in [Reference Cheung and Long1]) and may be attributed to incomplete de-embedding of the tapered feed lines used in the S-CPW prototype [Reference Cheung and Long1]. Nevertheless, these results indicate good agreement between simulation and measurement for further analysis. All further results are presented at 60 GHz. Although the specific values presented here may differ at other frequencies and with different BEOL process stacks, it is found that the observed trends are also present in literature where similar parametric variations are applied [Reference Horestani, Al-Sarawi and Abbott15, Reference Tang, Franc, Pistono, Siligaris, Vincent, Ferrari and Fournier21], though a systematic analysis to establish an optimal impedance for maximum Q-factor was not pursued in any of the prior studies.
Fig. 2. Broadband validation of parameter extraction method for S-CPW1.
Table 1. Comparison of simulated and measured S-CPW parameters at 60 GHz to validate simulation approach.
Propagation mode analysis
In this section, we compare the propagation modes of S-CPWs and S-MS lines, based on the layouts shown in Fig. 1. The electric and magnetic fields for each of these two lines are given in Figs 3(a)–3(d). Although the two media present similar magnetic field patterns, dissimilar electric field patterns are evident in Figs 3(a) and 3(c). However, if the location of the S-MS ground planes is modified, placing it coplanar with the signal strip, as shown in Figs 3(e) and 3(f), we obtain an electric field with a form similar to that of S-CPW. This leads to the conclusion that the S-CPWs studied in [Reference Cheung and Long1, Reference Franc, Pistono, Meunier, Gloria and Ferrari2] and the S-MS lines studied in [Reference Amin, Wang and Li5, Reference Kim and Nguyen7] propagate a very similar mode, despite the separate designations in prior literature. The distinguishing feature between the geometries is the width of the floating shield. For the transmission lines designated here (in keeping with prior literature [Reference Amin, Wang and Li5]) as S-MS, the width of the floating shield is narrower, modifying the linear capacitance and enabling variation of characteristic impedance by modifying its width. This is demonstrated in Section V.
Fig. 3. SWTL field lines (a) S-CPW – E-field, (b) S-CPW – H-field, (c) S-MS – E-field, (d) S-MS – H-field, (e) S-MS modified ground – E-field, (f) S-MS modified ground – H-field.
Results
With the validity of the simulation and extraction methods established by measurement, a large parametric simulation study was conducted. W GND = 25 μm and SS = SL = 0.7 μm are kept constant, while G GND is varied from 10 to 120 μm. To vary the characteristic impedance (Z 0), the signal strip width (W S) is varied (Table 2). This allows for a wide Z 0 tuning range, from which design rules may be derived. As some geometries may violate PDK layout rules multi-strips and dummy layout strategies may be required in some cases in order to implement these transmission lines.
Table 2. Signal conductor width ranges for different G GND values.
Figure 4 shows the 60-GHz Q-factor versus Z 0 for S-CPWs versus ground-to-ground spacing G GND and, consequently, required chip area. For comparison, standard CPWs of the same G GND are also simulated. The peak Q-factor for standard CPW increases up to G GND = 30 μm (reaching 14 for Z 0 = 69 Ω) and then decreases for larger G GND. This is due to the electric field that increasingly penetrates the lossy bulk silicon substrate as G GND increases. The narrow-gap S-CPW of G GND = 10 μm exhibits a Q-factor comparable to the best-performing standard CPW, though the S-CPW Q-factor increases as G GND increases, peaking above 30, similar to the trend observed in [Reference Tang, Franc, Pistono, Siligaris, Vincent, Ferrari and Fournier21].
Fig. 4. 60-GHz Q-factor versus Z 0 for CPW (dashed traces) and S-CPW (solid traces) for different G GND values.
In the same way, the Q-factor versus Z 0 for the S-MS lines of various Z 0 values is shown in Fig. 5. For comparison, a standard microstrip line is also considered, achieving a peak Q-factor of 15.6 for Z 0 between 45 and 55 Ω. The S-MS line has a lower Q-factor compared to standard microstrip for small G GND values but increases with increased G GND as is the case with the CPW versus S-CPW comparison.
Fig. 5. 60-GHz Q-factor versus Z 0 of S-MS line for different G GND values.
From the results in Figs 4 and 5, it is evident that the Z 0 for which peak Q-factor is achieved, lowers as G GND increases (see Fig. 6), both for S-CPWs and S-MS lines (similar to the trend observed in [Reference Horestani, Al-Sarawi and Abbott15]). The increase of the Q-factor when G GND increases is due to the increase in the width of the strip W s (see Fig. 6), which leads to a reduction in conductive losses, modeled by R strip. However, when W s becomes too large, for very low Z 0, the Q-factor decreases. This is mainly due to increase in the linear capacitance, as demonstrated in [Reference Franc, Pistono, Meunier, Gloria and Ferrari2], since the attenuation constant α is proportional to the frequency squared times the linear capacitance (second term of the right term of the equation):
with R strip the resistance of the strips (in Ω/m), R eddy the equivalent resistance due to the eddy current losses in the shielding strips (in Ω/m), R p the resistance of the shielding strips (in Ω ⋅ m), and L l and C l the linear inductance (in H/m) and linear capacitance (in F/m) of the transmission line, respectively.
Fig. 6. Maximum Q-factor at 60 GHz (left) and Z 0 at max Q-factor (right) of S-CPW and S-MS for various G GND values, with W S indicated for each Z 0 value.
For S-CPW, the Z 0 for peak Q-factor varies from 40 to 23 Ω, while the S-MS optimum Z 0 varies between 61 and 40 Ω. There is, therefore, no global optimal Z 0 for peak Q-factor in either medium, but rather an optimum for a given value of G GND.
Note that, when G GND is larger than 50 μm, the uncertainty of the extracted Q-factor increases for the SWTLs, manifesting as a ripple in the traces in Figs 4 and 5. This may be attributed to remeshing noise in the high aspect ratio shielding strips [Reference Lamecki, Balewski and Mrozowski22]. Despite this variation, the trend is clearly evident.
Figure 6 compares the peak Q-factor and the associated Z 0 for various G GND values. S-CPW achieves, on average, 12% higher Q-factor compared to S-MS. This is due to the higher sheet resistance of the reduced thickness M2 ground plane used for S-MS lines. The Z 0 associated with peak Q-factor equals 23 Ω and 43 Ω for S-CPWs and S-MS lines, respectively, indicating that so-called S-MS lines are preferred for Z 0 >40 Ω, and S-CPW for Z 0 <40 Ω.
For practical implementations, G GND >50 μm may be unacceptable, both because of the large occupied surface area as well as the resulting complexity of implementing T-junctions. Figure 7 shows the comparison of S-CPWs and S-MS lines for G GND ≤50 μm, where it is again evident that S-CPW reaches a peak Q-factor for lower Z 0 compared to S-MS, and that S-CPW has a higher overall peak Q-factor compared to S-MS. From Fig. 7, it can further be concluded that S-MS is preferred for Z 0 higher than ≈50–60 Ω if narrow transmission line width is required. This conclusion provides a valuable design guideline for CMOS designers wishing to integrate high Q-factor S-CPWs or S-MS lines in their circuits.
Fig. 7. Comparison of 60-GHz Q-factor for S-CPWs (blue) and S-MS lines (orange) for G GND ≤50 μm.
Conclusion
The propagation mode of S-CPW and S-MS have been analysed. It is found that the propagating modes are very similar, with S-MS exhibiting field patterns more similar to CPW than the microstrip field patterns described in [Reference Amin, Wang and Li5, Reference Kim and Nguyen7].
Next, the Q-factor of different on-chip transmission lines, as simulated in the AMS C35 process, have been evaluated as a function of their characteristic impedance. In general, the S-CPW is found to have a 12% higher Q-factor than S-MS lines in the same process. However, the Z 0 for which maximum Q-factor is achieved, reduces as the ground-to-ground spacing of the transmission lines increases, and differs between S-CPWs and S-MS lines. S-MS lines may, therefore, be preferred for certain values of Z 0, depending on the acceptable transmission line occupied surface area.
This analysis highlights the clear dependence between the transmission line characteristic impedance and Q-factor, and that the optimal Q-factor varies as the ground-to-ground spacing (and, subsequently, the on-chip area) changes. Future work will explore similar experiments for other kinds of CMOS slow-wave transmission lines, as well as derive suitable analytical or numerical models that capture the relationship between Z 0 and Q-factor.
Acknowledgements
The financial assistance of the South African Radio Astronomy Observatory (SARAO) (www.sarao.ac.za) and the National Research Foundation (NRF) of South Africa towards this research is hereby acknowledged. The authors wish to thank ANSYS for the academic licensing of Electronics Desktop 2019.2.
Johannes J.P. Venter received the B.Eng. degree in Electronic Engineering, and the B.Eng.Hons. degree in Microelectronic Engineering from the University of Pretoria, Pretoria, South Africa, in 2015 and 2016, respectively. He is currently pursuing a Ph.D. degree in Electronic Engineering with the same institution. Since January 2021, he serves as RF/MMIC Engineer at Multifractal Semiconductors (Pty) Ltd.
Anne-Laure Franc received the engineer and M.Sc. degrees from the Cergy-Pontoise University, Paris, France, in 2008 and the Ph.D. degree from the Grenoble University, France, in 2011. In 2012, she had a postdoctoral position with the Darmstadt University, Germany and she held a temporary lecturer and research assistant position in the Grenoble-Alpes University, Grenoble, France in 2013. Since September 2013, she has been an assistant professor with the University of Toulouse, France. Her research interests focus on the design, modelling and miniaturization of tunable microwave components.
Tinus Stander received the B.Eng. and Ph.D. degrees in electronic engineering from the University of Stellenbosch, Stellenbosch, South Africa, in 2005 and 2009, respectively. From 2010 to 2012, he served as RF and Microwave Engineer at Denel Dynamics (a division of Denel SOC, Ltd.). He joined the Department of Electrical, Electronic, and Computer Engineering, Carl and Emily Fuchs Institute for Microelectronics, University of Pretoria, in 2013. He currently serves as a Principal Investigator in microwave and millimeter-wave microelectronics at the Institute, with personal research interest in the application of distributed passives on-chip and built-in self-testing. He is also registered as Professional Engineer with the Engineering Council of South Africa and serves as a Scientific Advisor with Multifractal Semiconductors (Pty) Ltd.
Philippe Ferrari received the Ph.D. degree from the “Institut National Polytechnique de Grenoble” (INPG), France, in 1992, with honors. Since 2004, he is a professor at the University Grenoble Alpes, Grenoble, France. His main research interest concerns tunable and miniaturized devices, such as filters, phase shifters, matching networks, couplers, power dividers and VCOs. These devices are developed in many technologies, PCB, CMOS/BiCMOS, and nanowires, at RF and mm-wave frequencies. He has worked towards the development of slow-wave CPW, and developed new topologies of slow-wave transmission lines, based on microstrip lines and SIWs, respectively. He is author or co-author of more than 230 papers published in international journals or conferences, and co-holder of six patents. He is an IEEE senior member, a member of the Editorial Board of the International Journal on RF and Microwave Computer-Aided Engineering (Wiley), an Associate Editor of the International Journal of Microwave and Wireless Technologies (EuMA) and member of the Editorial Board of Electronics Letters.
