II. DESIGN

A conventional LHTL based on an artificial transmission line with interdigital capacitors and shunt inductors is shown in Fig. 1 [Reference Caloz and Itoh8]. A LHTL can be realized artificially in the form of a lumped-element ladder network. In this model, there is no series parasitic inductance because the parasitic inductance is small enough. There is a parasitic capacitance present in the interdigital capacitor.

Fig. 1. (a) The figure and (b) the equivalent circuit model of a conventional unit delay line based on an artificial LHTL.

The propagation factor with the parasitic capacitance β _p is given by

(1)$$\beta _P = - \displaystyle{{\sqrt {1 - \omega ^2 L'C_g } } \over {\omega \sqrt {L'C'} }} = - \displaystyle{1 \over {\omega \sqrt {L_p C'} }} = \beta \cdot \sqrt \xi .$$

Here, ω denotes the angular frequency, L′ is the unit length inductance, C′ is the unit length capacitance, and C _g is the parasitic capacitance per unit length:

(2)$$L_P = \displaystyle{{L'} \over \xi }.$$

(3)$$\xi = 1 - \omega ^2 L'C_g.$$

The characteristic impedance with the parasitic capacitance, Z _{0_P}, is given by

(4)$$Z_{0\_P} = \sqrt {\displaystyle{{L'} \over {C'}} \cdot \displaystyle{1 \over {1 - \omega ^2 L'C_g }}} = \sqrt {\displaystyle{{L_P } \over {C'}}} = Z_0 \cdot \displaystyle{1 \over {\sqrt \xi }}.$$

The time delay with the parasitic capacitance, t _{d_P} is given by

(5)$$t_{d\_P} = \displaystyle{1 \over {\omega ^2 \sqrt {L_p C'} }} = t_d \cdot \sqrt \xi.$$

The operating frequency is limited by the parasitic capacitance, as follows:

(6)$$\displaystyle{1 \over {2\sqrt {L'C'} }} \le \omega \le \displaystyle{1 \over {2\sqrt {L'C_g } }}.$$

The effects of the parasitic capacitance known through equations (1)–(5) show an increasing impedance mismatch and a reduced the time delay in the range of equation (6).

The proposed LHTL with a ground slot that reduces the parasitic capacitance is shown along with the equivalent circuit model in Fig. 2. The parasitic C _g can be reduced by removing the ground metal under the interdigital capacitor. Capacitances and inductances are determined to have a 50 Ω port impedance and a small dispersion at a center frequency of 24 GHz. The test structures consist of the three-unit LHTL delay lines and 50 Ω lines that connect the connectors at each side. The test structures are designed on an RO3003 PCB, which has a dielectric constant of 3 and a thickness of 10 mil.

Fig. 2. (a) The figure and (b) the equivalent circuit model of the proposed delay line based on parasitic reduced artificial LHTL.

III. MEASUREMENT RESULTS

Conventional LHTL delay lines and the proposed delay lines with ground slots were measured with a short-open-load-through calibration up to the connectors to measure the S parameter. An Agilent 8510C vector network analyzer was used. The input return loss of proposed LHTL is shown in Fig. 3. The input return loss of the parasitic reduced LHTL is less than −10 dB from 20.5 to 26.1 GHz. The measured time delays of conventional LHTL and the proposed structures are shown in Fig. 4. The 50 Ω line which has same length of 50 Ω line for connecting to the connectors in each side is also fabricated and measured. The time delay of proposed LHTLs with ground slots is approximately 78 psec at 24 GHz. The time delay of the proposed parasitic reduced LHTL is higher by approximately 45 psec at 24 GHz compared to a conventional LHTL. These results are also in accordance with equation (5).

Fig. 3. Measured return losses of the three-unit LHTL with and without a ground slot.

Fig. 4. Measured time delay of the test patterns of the proposed three-unit LHTL and that of a conventional LHTL.