I. INTRODUCTION
While silicon-based technologies have become competitors in the millimeter-wave arena [Reference Cressler1–Reference Shigematsu, Hirose, Brewer and Rodwell5], the continued scaling of silicon processes, in order to increase f T/f MAX, has lowered bias voltages and therefore output voltage swings of silicon power amplifiers (PAs), from one process generation to the next [Reference Rieh, Greenberg, Stricker and Freeman6]. Low RF output power has been a large contributing factor in stifling silicon-based technologies to provide commercial single-chip millimeter-wave solutions [Reference Wang7, Reference Rieh8]. In an attempt to counter the effects of lowered bias voltages, two approaches are commonly used to increase the radio frequency (RF) output power of silicon-based PAs: device paralleling and power combining [Reference Farmer, Darwish and Zaghloul9].
While the paralleling of transistors increases the RF output current swing of the amplifier, and therefore, the RF output power, it lowers the output impedance of the amplifier and increases the quiescent current flow in Class A amplifiers, having an impact on power added efficiency (PAE). On chip power combiners, passive or active, can lead to large chip area, RF power loss, and poor power density. In this paper, a third approach to increase RF output power is discussed, implemented in silicon at millimeter wave, and its measurements presented. The approach, called the high-voltage/high-power (HiVP) configuration, increases the RF output voltage swing of the amplifier, increases the output impedance, and allows for a customizable bias for the designer, ensuring a configuration that can be used from one process generation to the next [Reference Ezzeddine and Huang10].
II. CONCEPT
A) DC perspective
The schematics for a two-stage and three-stage silicon germanium (SiGe) heterojunction bipolar transistor (HBT) HiVP are shown in Figs 1(a) and 1(b), respectively. For clarity, the schematics are shown without input or output matching circuitry. From a DC perspective HBTs Q 1−2 (for the two-stage device) and HBTs Q 1−3 (for the three-stage device) are stacked in a cascode fashion, essentially in DC series. The total DC bias becomes V CC = N (the number of transistors in the stack) × V CE (for an individual transistor). The bases of transistor's Q 1−N are biased from the single V CC supply, through a corresponding resistor-ratioed current mirror stack formed by Q B1−BN and R 1(A&B)–N(A&B). The operation of the current mirror will be discussed later, but it is sufficient to say the devices in Q 1−N will provide the RF amplification and Q B1−BN will provide DC bias.
Fig. 1. (a, b) Two-stage SiGe HBT HiVP (a – left) and three-stage SiGe HBT HiVP (b – right).
B) RF perspective
What differentiates this configuration from the classic cascode configuration is the size of the base capacitors (C 1−N) in Figs 1(a) and 1(b). The base capacitors are not large enough to act as a signal ground, essentially leaving each of the bases floating. Instead, they are sized to a first-order approximation using equation (1), where C 1is the base capacitor and C be is the internal base–emitter capacitance of the HBT [Reference Farmer, Darwish and Zaghloul9]. The role of the base capacitor is to adjust the emitter impedance of the transistor it is attached to. By adjusting the impedance seen at the transistor's emitter, it can be set to act as the optimal load to the collector of the transistor that precedes it. Using Fig. 1(a) as an example, C 1 is sized to ensure Z emitter of Q 2 is equal to optimal load for Q 1. Once this tuning is achieved in simulation, the RF signal exiting Q 1 will be optimally transferred to the emitter of Q 2, in effect transistors Q 1−N, will be in RF series as well as DC series:
The final component of the HBT HiVP configuration is the feedback resistor (R F) shown in both Figs 1(a) and 1(b). The function of R F is to provide a current reference for the resistor-ratioed current mirror. Under RF power, R F ensures that the current reference to the mirror swings up and down with the collector voltage of the top transistor Q N. This enables a maximum output voltage swing of twice V CC. In addition, it prevents the breakdown (BV CBO) of each transistor by ensuring that each transistor is constantly biased in saturation, as the RF output voltage of the amplifier swings up and down.
C) Resistor-ratioed current mirror
A current mirror allows for precise control over the base current that biases the SiGe HBTs in the main stack (Q 1−N) in Figs 1(a) and 1(b). A resistor-based voltage ladder will not work well for SiGe HBT devices as they are extremely sensitive to very small fluctuations in base–emitter voltage [Reference Ezzeddine and Huang10]. Any mismatch in resistor sizes to due fabrication error would result in transistors in the main stack having different bias points. In Figs 1(a) and 1(b), the transistors in the main stack (Q 1−N) are of identical emitter area to ensure the same DC current flow in the stack. The transistors in the bias stack (Q B1−BN) also have identical emitter area to one another, but that area is set at a ratio of 1:5 to the emitter area of the transistors in the main stack. Each transistor in the stack is biased via a corresponding resistor-ratioed current mirror. Transistors Q 1 and Q B1 from Figs 1(a) and 1(b) are enlarged in Fig. 2. In Fig. 2, Q B1 has 1/5 the emitter area of Q 1. The 1:5 ratio is to some extent arbitrary; the smaller the ratio, the higher the PAE of the amplifier will become, but the limit will depend on transistor emitter area sizes available in the process design kit. Therefore careful consideration of design goals must be used in determining the ratio.
Fig. 2. Resistor-ratioed current mirror.
The resistors in the mirror must be in the same ratio as the transistor's emitter areas. In Fig. 2, resistor R 1A is five times larger than R 1B, ensuring that five times the current will be provided to transistor Q 1 as Q B1. The ratio allows the use of a far smaller transistor than a traditional current mirror, decreasing both the area of the bias stack and the quiescent current for the bias stack, having the effect of increasing the amplifier's PAE. The ratio of resistors guards against potential fabrication errors, ensuring that an exact size is not necessary as long as the ratio is correct, thus lowering the area of the resistors needed, as tight tolerance resistors typically have large areas in most design kits.
III. IMPLEMENTATION
Originally implemented in GaAs MESFETs (MEtal Semiconductor Field Effect Transistor) at 3.5 GHz [Reference Ezzeddine and Huang10], and more recently in SiGe HBTs at 2.4 GHz [Reference Farmer, Darwish and Zaghloul9], the HiVP configuration discussed in this paper has been implemented using SiGe HBTs at millimeter wave, with a center frequency of 30 GHz – a frequency of interest for the sponsors of this work. For both the two-stage and three-stage amplifiers, double-stripe-high-f T SiGe HBTs with emitter area of 18 µm × 120 nm were used in the main transistor stacks, whereas single-stripe-high-f T SiGe HBTs with emitter area of 3.46 µm × 120 nm were used in the bias stacks.
The DC, small signal, harmonic balance simulation techniques outlined earlier [Reference Farmer, Darwish and Zaghloul9] were used to design the two- and three-stage stacks in this work. Figure 3(a) shows the dynamic-load-line simulation for a single SiGe HBT. Figures 3(b) and 3(c) show the dynamic-load-line simulations for the two-stage and three-stage amplifiers. Figure 3(a) shows that the RF output voltage swing for a single SiGe HBT with an optimal load is approximately 1.4 V. Figure 3(b) shows that the RF output voltage swing for the two-stage amplifier is approximately 2.2 V, while the output voltage swing for the three-stage amplifier in Fig. 3(b) is 4.5 V. The saturated output power of the amplifiers was measured at 5.41 and 8.85 dBm, respectively, which was a 2.2-fold increase in output power, due to the approximately two-fold increase in output voltage swing, achieved through the addition of one stage.
Fig. 3. (a–c) Dynamic load line simulations, one-stage (a – top), two-stage (b – bottom left), and three-stage (c – bottom right) SiGe HiVPs.
The optimal loads for the single HBT, the two-stage, and three-stage amplifier are 43.74 + j53, 110 + j30, and 120 + j45 Ω, respectively. As each stage is added the output impedance is increasing as expected.
The CAD layout and fabricated microphotograph of the two-stage SiGe HBT HiVP is shown in Figs 4(a) and 4(b), respectively. The values for the components in Figs 4(a) and 4(b) are listed in Table 1. The layout is the implementation of the schematic in Fig. 1(a), with a 0.1 nH inductor inserted between Q 1's collector and Q 2's emitter. The inductance was necessary to further adjust Q 2's emitter impedance, as Q 2's base capacitor could not provide enough tuning range to reach the optimal impedance required by Q 1's collector. This inductance was split into two 0.2 nH inductors in parallel in order to ensure symmetry. In future layouts, it is recommended that a small length of thick metal replaces the large area inductances. In this work, a parameterized inductor cell was used to avoid EM simulation to verify the accuracy of the process design kit provided by the foundry models.
Fig. 4. (a, b) CAD layout (a – left) and microphotograph (b – right) of two-stage SiGe HiVP; X = 400 µm × Y = 170 µm.
Table 1. Component values for two-stage SiGe HiVP.
The CAD layout and fabricated microphotograph of the three-stage SiGe HBT HiVP is shown in Figs 5(a) and 5(b), respectively. The values for the components in Figs 5(a) and 5(b) are listed in Table 2. No inductance was necessary between stages 1 and 2, as in the two-stage design, as the optimal load impedance was adequately met by stage 2 with only the base capacitor C 1. This led to the even smaller layout area and also increased the power density of the circuit.
Fig. 5. (a, b) CAD layout (a – left) and microphotograph (b – right) of three-stage HiVP circuit, X = 60 µm × Y = 200 µm.
Table 2. Component values for three-stage SiGe HiVP.
IV. MEASUREMENTS
For the two-stage device both the small and large signal measurements were made with V CC = 2.2 V and I C = 12.8 mA. For the three-stage device, all measurements were made with V CC = 3.28 V and I C = 14.3 mA. The simulated versus measured small signal measurements for the two-stage and three-stage SiGe HBT amplifiers with 50 Ω terminations are shown in Figs 6(a) and 6(b), respectively. It should be noted that no matching circuitry was integrated on-chip; a custom impedance was desired by the designer for eventual integration of these amplifiers into a power combining structure. At 30 GHz, the two-stage device small signal gain was measured at 7.96 dB, whereas the three-stage device measured 11.18 dB.
Fig. 6. (a, b) S-parameters for two-stage (a – left) and three-stage (b – right); red – sim., blue – meas.
The large signal simulation and measurements at 30 GHz for the two-stage device are shown in Figs 7(a) and 7(b), respectively. The measurements were made using a load-pull measurement system, where the optimal source and load impedance were characterized and presented to the device for optimal output power. With an area of only 0.068 mm2, at 30 GHz, the 1-dB compressed output power was measured at 3.37 dBm with a PAE of 6.14%, whereas saturated power was measured at 5.41 dBm with a PAE of 8.06%. It is expected that PAE would decrease slightly when the device is matched to 50 Ω due to losses in the matching circuit.
Fig. 7. (a, b) Power characteristics for two-stage device (a – left) simulation (b – right) measurements at 30 GHz.
The large signal simulation and measurements at 30 GHz for the three-stage device are shown in Figs 8(a) and 8(b), respectively. The measurements' optimal source and load impedance were characterized and presented to the device for optimal output power. With an area of only 0.12 mm2, at 30 GHz, the 1-dB compressed output power was measured at 3.32 dBm with a PAE of 5.3%, whereas saturated power was measured at 8.85 dBm with a PAE of 11.35%. It should be noted that while the 11.35% PAE was achieved at 8 dB of compression, the 8 dB is shared across the three stages of the HiVP stack resulting in 8 dB/3 stages = 2.6 dB per stage, a safe operating region for each of the underlying amplifiers.
Fig. 8. (a, b) Power characteristics for three-stage device (a – left) simulation (b – right) measurements at 30 GHz.
Figure 9 shows P − 1 dB versus frequency for the three-stage device. P − 1 dB was plotted for frequencies: 10–35 GHz in 10 GHz steps. The figure shows the simulated versus measured values of P − 1 dB with 50 Ω terminations at each frequency and not the idea load. As one might expect the simulated values (shown in red) are higher than measured values (shown in blue) as is typically the case for the large signal model of silicon-based processes. The purpose of this measurement is to show the bandwidth of the PA across a wide frequency range.
Fig. 9. P − 1 dB versus frequency for three-stage device (red) simulation (blue) measurements W/50 Ω terminations.
V. CONCLUSION
A two- and three-stage SiGe HBT HiVPs have been designed, fabricated, and measured in a 0.12 µm commercial SiGe bipolar complementary metal oxide semiconductor (BiCMOS) process. Although EM tools were used to optimize the layout, the foundry provided models have provided fairly accurate prediction of the final results obtained in measurement. The simulation techniques followed were the procedures outlined in [Reference Farmer, Darwish and Zaghloul9]. Measured results of 11.18 dB of small signal gain – 8.85 dBm of saturated output power with a PAE of 11.35% – have been achieved in only 0.012 mm2 of area using the SiGe HBT HiVP configuration. We found very good agreement between simulation and measurement in both small and large signal characterizations. The work presented in this paper represents an initial successful attempt at the use of the HiVP configuration at across a wide band of millimeter-wave frequencies. It is intended to provide verification of the architecture at high frequencies, and offers the silicon designer a simple alternative for increasing output power density, output impedance, and bias over conventional methods available in the literature.
ACKNOWLEDGEMENTS
This work was supported in part by The George Washington University (GWU), The Achievement Rewards for College Scientists (ARCS), and by an appointment to the US Army Research Laboratory Postdoctoral Fellowship Program administered by the Oak Ridge Associated Universities through a contract with the US Army Research Laboratory.
Thomas J. Farmer received his B.S and M.S. degrees in computer science from the City University of New York, in 1998 and 2002, respectively, and his Ph.D. degree from The George Washington University in 2010. Prior to return for his doctoral work, from 1998 to 2004, he worked as a software engineer for AT&T Laboratories in Middletown, NJ as a Member of Technical Staff. Dr. Farmer has held several teaching and teaching assistant positions at The George Washington University (GWU) since 2004, for which he received the Philip Amsterdam Excellence in Teaching Award in 2008. He was named a fellow of the Achievement Rewards for College Scientists (ARCS) Foundation in 2008. Dr. Farmer is currently a postdoctoral fellow in the RF and Electronics Division at the US Army Research Laboratory (ARL) in Adelphi, MD and an Adjunct Professor at The George Washington University in Washington, DC.
Ali Darwish received his B.Sc. and M.S. degrees in electrical engineering (Honors) from the University of Maryland at College Park, in 1990 and 1992, respectively, and his Ph.D. degree from the Massachusetts Institute of Technology (MIT), Cambridge, in 1996. In 1990, he joined COMSAT Labs, where he conducted the experimental work for his M.S. thesis. In 1992, he was Research Assistant in the Optics and Quantum Electronics Group at MIT. In 1997, he co-founded Amcom Communications, Inc., a leading supplier of high-power microwave devices. In 2003, he joined the US Army Research Laboratory (ARL), Adelphi, MD, where he conducted research on wide bandgap materials (GaN), thermal analysis, and novel monolithic-microwave integrated-circuit concepts. In 2007, he joined the American University in Cairo, New Cairo, Egypt, as an Assistant Professor and was promoted to Associate Professor in 2009. Dr. Darwish was awarded the National Science Foundation (NSF) Fellowship.
Benjamin Huebschman received his B.S. degree from Purdue University, West Lafayette, IN, his M.S. and Ph.D. degrees from the University of Maryland at College Park, in 2002 and 2010, respectively. Currently, he is with the US Army Research Laboratory (ARL), Adelphi, MD. His areas of interests include high-frequency, high-power amplifiers, and semiconductor physics.
Edward Viveiros received his B.S.E.E. degree from Rutgers University, Piscataway, NJ, in 1984 and his M.S.E.E. degree from The John Hopkins University, Baltimore, MD, in 1991. He is a team leader in the RF Electronics Branch at the US Army Research Laboratory (ARL), Adelphi, MD, currently, leading R&D efforts in advanced device, circuit, and integration technologies, including gallium–arsenide, indium–phosphide, gallium–nitride, silicon–germanium microelectromechanical systems for SATCOM, radar, and multifunction RF applications.
Mona E. Zaghloul received her B.S. degree from Cairo University, Cairo, Egypt, in 1965, and her M.S. degree in science, a second M.S. degree in math, and her Ph.D. degree from the University of Waterloo, Waterloo, ON, Canada, in 1970, 1971, and 1975, respectively. She is currently a Professor of Electrical and Computer Engineering at The George Washington University (GWU), Washington, DC, where she is also director for the Institute for MEMS and VLSI Technology. She has published over 270 technical papers in the general areas of circuits and systems, microelectronics system design, VLSI circuits design, sensors design, and microelectromechanical systems. She has also contributed to several books. Since 1984, she has been with the National Institute of Standards and Technology (NIST), Semiconductor Electronics Devices Division, Gaithersburg, MD. She was the President of the IEEE Sensors Council for the years 2008–2009. Dr. Zaghloul is a Fellow of the IEEE.
