II. DYNAMIC SUPPLY OF THE PA WITH SLOW VERSIONS OF THE SIGNAL'S ENVELOPE

In an ET system (see Fig. 1), the supply voltage is dynamically adjusted to track the RF envelope at high instantaneous power. The supply voltage can be shaped according to different criteria. By means of a so called shaping function it is possible to accommodate the shape of the supply voltage (that somehow must follow the instantaneous RF envelope) to achieve the following objectives: optimum efficiency, isogain [Reference Wimpenny11–Reference Hoversten, Schafer, Roberg, Norris, Maksimovic and Popovic13] or SR and BW reduced shaping [Reference Vizarreta, Montoro and Gilabert14].

Fig. 1. General block diagram of an ET PA with DPD.

Focusing on this later objective, two different approaches based on SR and BW reduction of the RF signal's envelope showed that these strategies are suitable to adapt the envelope characteristics to the EA requirements or limitations at the expenses of having efficiency degradation. On the one hand, the method proposed in [Reference Jeong, Kimball, Kwak, Hsia, Draxler and Asbeck5, Reference Mustafa, Bassoo and Faulkner6] limits the BW of the envelope iteratively, which may represent an issue in real time applications. On the other hand, the method proposed in [Reference Montoro, Gilabert, Bertran and Berenguer8] consists of a real-time algorithm where the resulting signal is limited in SR but not in BW, making challenging its amplification if only a switched mode EA is considered or requiring a wide band if only a linear EA is considered. Therefore, in [Reference Vizarreta, Montoro and Gilabert14], the SR reduction algorithm proposed in [Reference Montoro, Gilabert, Bertran and Berenguer8] was modified in order to also restrict the BW of the resulting slow envelope. Moreover, due to its simplicity this algorithm is suitable to be implemented in a digital signal processor. Fig. 2 shows the original RF signal's envelope, an SR reduced version of the original envelope (SR reduced envelope – SRRE) and a BW reduced version of the original envelope (BW reduced envelope – BWRE) in both time and frequency domains, respectively. The parameter N (defined in [Reference Montoro, Gilabert, Bertran and Berenguer8]) is related to the maximum allowed increment in the signal's slope. For example, N = 100 corresponds to an SR reduction of 96% and BW reduction of 64% with respect to the original signal's envelope. The results shown in Fig. 2 were extracted from the implementation of this algorithm on a FPGA Virtex-4 whose clock speed was set to 60 MHz.

Fig. 2. Waveforms and spectra of the envelope and its SR and BW limited versions [14].

As reported in [Reference Gilabert, Montoro and Vizarreta15], the efficiency decays more or less linearly with the BW reduction, while it presents a logarithmic behavior with the SR reduction. As a consequence, when considering applications with high BW signals (e.g. dual-band transmissions) it is possible to find a trade-off solution to meet both SR and BW requirements of the EA while still keeping a reasonably good drain efficiency figure.

Unfortunately, using the SR and BW limited envelope (or simply slow envelope – E _s) to supply the power transistor's drain generates a particular nonlinear distortion. Fig. 3 shows the AM–AM characteristics considering different margins of E _s values. As observed in Fig. 3, the ET PA shows a nonlinear variant gain because the slow envelopes used to supply the PA and the RF input signal are not univocally related. Therefore, for a given input it is possible to have a range of different outputs because it depends on the specific value of the dynamic power supply. Therefore, the ET PA presents a SED nonlinear behavior.

Fig. 3. AM–AM characteristics of the PA when considering only three margins of E _s (left) and taking into account all possible values of E _s (right).

III. DESIGN OF A REAL-TIME DPD FOR ET

The type of low-pass equivalent black-box behavioral model required to characterize the nonlinear distortion that arises when applying ET is dependent on the strategy (or shaping function) followed to supply the PA. Therefore, on the one hand, if the PA drain voltage follows the same shape (despite being bounded at low-voltage levels) than the RF signal's envelope, typical behavioral models such as the memory polynomial (MP) [Reference Kim and Konstantinou7] can be used for DPD purposes. On the other hand, if the slow envelope is used to supply the PA, then the DPD has to include the information of the slow envelope in order to be capable of compensating for this type of nonlinear distortion.

For the case of using the original envelope, we can consider the implementation of a DPD based on the simple MP model. Following the notation in Fig. 1, the input–output relationship of the MP DPD is defined as

(1)$$x [n] =\sum\limits_{i=0}^N {u [n - \tau _i ] f_i \left({\left\vert {u [n - \tau _i ] } \right\vert } \right)}\comma \;$$

where nonlinear functions f _i(·) can be described by polynomials of order P

(2)$$\eqalign{f_i \left({\left\vert {u [n - \tau _i ] } \right\vert } \right) &=\sum\limits_{p=0}^P {\gamma _{pi} \left\vert {u [n - \tau _i ] } \right\vert ^p }=\gamma _{0i}+\gamma _{1i} \left\vert {u [n - \tau _i ] } \right\vert \cr & \quad +\cdots+\gamma _{Pi} \left\vert {u [n - \tau _i ] } \right\vert ^P.}$$

As previously explained, when considering the slow envelope to supply the PA, the nonlinear distortion that appears cannot be compensated by simply using dynamic behavioral models such as the MP [Reference Montoro, Gilabert, Berenguer and Bertran10]. Therefore, in [Reference Gilabert and Montoro9] a dynamic SED behavioral model is proposed to compensate for this type of nonlinear distortion. The input–output relationship of the SED-DPD is defined as

(3)$$x [n] =\sum\limits_{j=0}^M {\sum\limits_{q=0}^Q {\sum\limits_{i=0}^N {\sum\limits_{p=0}^P {\gamma _{piqj} \left({E_s [n - \tau _j ] } \right)^q } } } } u [n - \tau _i ] \left\vert {u [n - \tau _i ] } \right\vert ^p\comma \;$$

where E _s[n] is the SR-limited version of the original envelope, u[n] is the input signal, τ_j and τ_i (with τ₀ = 0) are the most significant tap delays of the slow envelope and input signal, respectively, contributing to the characterization of memory effects.

Figure 4 shows linearized and unlinearized AM–AM characteristics of an ET PA when supplying the PA with the original envelope (MP DPD used) and with a slower version of the original envelope (SED-DPD used). The linearity performance in terms of out-of-band distortion compensation of the SED-DPD can be observed in Fig. 5. These particular results were measured on a test-bed based on instrumentation, schematically depicted in Fig. 1 and described in [Reference Montoro, Gilabert, Berenguer and Bertran10]. The Device under test (DUT) is a Cree Inc. Evaluation Board CGH40006P-TB (GaN transistor) at 2 GHz operating at a mean output power of 28 dBm. For the sake of simplicity, a linear IC LT1210 was considered as the envelope driver. The PAPR of the signals at baseband range from around 8 up to 11 dB, depending on the type of signal used (single-carrier M-QAM or OFDM). In the case of the SED-DPD, we used the following configuration: P = 9, Q = 2, M = 3 and N = 1 (alternatively, N = 0).

Fig. 4. Linearized and unlinearized AM-AM characteristics of an ET PA considering: (a) the original envelope (left), (b) a slow envelope (right).

Fig. 5. Unlinearized and linearized (dynamic SED-DPD) output power spectra of a single-carrier 16-QAM (left) and OFDM 16-QAM (right) signals, respectively.

IV. FPGA IMPLEMENTATION ARCHITECTURES

The FPGA implementation of an MP DPD will follow the structure presented in Fig. 6. Each branch represents one nonlinear function expressed by means of a polynomial development. To allow an accurate and efficient FPGA implementation of the MP DPD it is important to minimize the number of arithmetic operations (counting both additions and multiplications) and minimize the accumulative error inside the FPGA. Both issues can be addressed using the Horner's rule and this way limiting the number of consecutive complex multiplications to a maximum of two. Moreover, as presented in [Reference Mrabet, Mohammad, Mkadem, Rebai and Boumaiza16], in order to avoid a large variation in magnitude of the polynomial coefficients (which requires a large number of bits to preserve the precision of the computation) it is possible to take the ratios of adjacent coefficients. As a consequence, with a reformulation of (2) according to Horner's rule, nonlinear functions f _i(·) can be described as

(4)$$\eqalign{&f_i \left({\left\vert {u [n - \tau _i ] } \right\vert } \right)=\gamma _{0i} \left(1+\displaystyle{{\gamma _{1i} } \over {\gamma _{0i} }}\left\vert u [n - \tau _i ] \right\vert \left(1+\cdots\right. \right. \cr & \quad \left. \left. +\displaystyle{{\gamma _{\left({P - 1} \right)i} } \over {\gamma _{\left({P - 2} \right)i} }} \left\vert {u [n - \tau _i ] } \right\vert \left(1+\displaystyle{{\gamma _{Pi} } \over {\gamma _{\left({P - 1} \right)i} }}\left\vert {u [n - \tau _i ] } \right\vert \right)\right)\cdots \right)}$$

Fig. 6. Block diagram of the MP DPD (left) and the SED-DPD (right).

Therefore, taking into account the polynomial expression in (2), where $\gamma _{pi} \in {\open C}$, it takes p + 1 real multiplications for each monomial $\gamma _{pi} \left\vert {u [n - \tau _i^{} ] } \right\vert \, ^p $ and 2P additions (P complex additions), resulting in P(P+7)/2 arithmetic operations for a polynomial of degree P. While using the formulation in (4), computation starts with the innermost parentheses using the coefficients of the highest degree monomials and works outward, each time multiplying the previous result by $\left\vert {u [n - \tau _i] } \right\vert $ and adding the coefficient of the monomial of the next lower degree. Now it takes 4P arithmetic operations for a polynomial degree of P, which for high polynomial orders, Horner's algorithm results much more computationally efficient. Figure 7 shows the structure of the nonlinear branches of the MP DPD in Fig. 6. Alternatively, instead of using polynomials to describe nonlinear functions f _i(·) it would have been possible to use basic predistortion cells (BPCs) [Reference Gilabert, Montoro and Bertran17]. A BPC is composed of a RAM block acting as a look-up table (LUT), an address calculator and complex multipliers.

Fig. 7. Structure of one of the branches of the MP DPD (see Fig. 6) using Horner's rule.

In order to implement the dynamic SED-DPD in an FPGA device, the polynomial model in (3) is expressed as a combination of several BPCs [Reference Gilabert and Montoro9]:

(5)$$\eqalign{x [n] & =u [n] \times \underbrace {\sum\limits_{p=0}^P {\gamma _{p000} \times \left\vert {u [n] } \right\vert ^p } }_{G_{LUT}^{000} \lpar{\cdot}\rpar }+\cdots+\left({E_s [n] } \right)^Q \cr &\quad \times u [n] \times \underbrace {\sum\limits_{p=0}^P {\gamma _{p0Q0} \times \left\vert {u [n] } \right\vert ^p } }_{G_{LUT}^{0Q0} \lpar{\cdot}\rpar }+\cdots +u [n] \cr &\quad\times \underbrace {\sum\limits_{p=0}^P {\gamma _{p00M} \times \left\vert {u [n] } \right\vert ^p } }_{G_{LUT}^{00M} \lpar{\cdot}\rpar }+\cdots+\left({E_s [n - \tau _M ] } \right)^Q \cr &\quad \times u [n] \times \underbrace {\sum\limits_{p=0}^P {\gamma _{p0QM} \times \left\vert {u [n] } \right\vert ^p } }_{G_{LUT}^{0QM} \lpar{\cdot}\rpar }+\cdots \cr &\quad+u [n - \tau _N ] \times \underbrace {\sum\limits_{p=0}^P {\gamma _{pN00} \times \left\vert {u [n - \tau _N ] } \right\vert ^p } }_{G_{LUT}^{N00} \lpar{\cdot}\rpar }\cr &\quad +\cdots+\left({E_s [n] } \right)^Q \,\times\, u [n - \tau _N ]] \cr &\quad \times \underbrace {\sum\limits_{p=0}^P {\gamma _{pNQ0} \times \left\vert {u [n - \tau _N ] } \right\vert ^p } }_{G_{LUT}^{NQ0} \lpar{\cdot}\rpar }+\cdots \cr &\quad+u [n - \tau _N ] \times \underbrace {\sum\limits_{p=0}^P {\gamma _{pN0M} \times \left\vert {u [n - \tau _N ] } \right\vert ^p } }_{G_{LUT}^{N0M} \lpar{\cdot}\rpar }\cr &\quad +\cdots+\left({E_s [n - \tau _M ] } \right)^Q \,\times\, u [n - \tau _N ] \cr &\quad \times \underbrace {\sum\limits_{p=0}^P {\gamma _{pNQM} \times \left\vert {u [n - \tau _N ] } \right\vert ^p } }_{G_{LUT}^{NQM} \lpar{\cdot}\rpar }+\comma \;}$$

which yields to the following expression of the SED-DPD:

(6)$$x [n] =\sum\limits_{j=0}^M {\sum\limits_{q=0}^Q {\sum\limits_{i=0}^N {\left({E_s [n - \tau _j ] } \right)^q } } u [n - \tau _i ] \times G_{LUT}^{iqj} \left({\left\vert {u [n - \tau _i ] } \right\vert } \right)}$$

with G _LUT^iqj being complex LUT gains.

Figure 6 shows the general block diagram of the SED-DPD architecture, where nonlinear functions f _iqj (·) can be expressed as a combination of BPCs. The number of BPCs forming this SED-DPD is # BPCs = (Q + 1)(N + 1)(M + 1). This structure requires less arithmetic operations than using polynomials; however, it consumes more memory resources.

Figure 8 shows the basic structure of a BPC where a dual-port RAM, with two independent sets of ports for simultaneous reading and writing, is used to allow the complex LUT gains to be updated continuously without interrupting the normal data transmission. Therefore, because of this LUT-based architecture, it is possible to perform continuous adaptation of the DPD function by means of the least-mean squares (LMS) algorithm [Reference Gilabert, Montoro and Bertran17].

Fig. 8. Basic architecture of a BPC forming the SED-DPD (see Fig. 6).