II. CIRCUIT DESIGN

The 120 GHz chipset comprises a signal-generation chip and a dual–transceiver (TRX) chip. The signal-generation chip includes a voltage-controlled oscillator (VCO) with fine-and coarse-tuning capability, an output buffer, and a prescaler with a total division ratio of eight. A similar topology can be found in [Reference Jahn, Stelzer and Hamidipour2]. The block diagram of the TRX die is depicted in Fig. 1. It includes two TRX cells: the first cell features a single TRX port and favors the monostatic radar configuration which uses a single antenna for transmit (TX) and receive(RX); therefore, a duplexer (Rat-race coupler) was introduced to separate signals into TX and RX. The second TRX cell deploys separate TX and RX channels, and favors a radar architecture with separate TX and RX antennas. If the distance between the antennas is of the order of the wavelength the setup is said to be quasi-monostatic. If the TX and RX antennas are located at different positions and the distance in between is very large compared to the wavelength, the configuration is referred to as bistatic (used, e. g., in military applications and weather radar). Obviously, there is no need for a duplexer in the quasi-monostatic approach, since the TX and RX signals are separated by different antennas. For this reason, higher output power, improved RX gain, and lower RX noise figure (NF) can be observed compared to the monostatic approach, where the duplexer leads to a degradation of the aforementioned figures (≈4.5 dB, cf. [Reference Jahn, Stelzer and Hamidipour2]). Furthermore, the quasi-monostatic approach can mitigatethe dc-offset problem in zero-IF receivers, which originates from TX leakage, strong reflections of mismatched interfaces such as bond–wire transitions, and antenna mismatch [Reference Jahn, Wagner and Stelzer8].

Fig. 1. Block diagram of the integrated dual TRX chip. It comprises two slightly different TRX cells that favor monostatic and quasi-monostatic radar configurations, respectively. The building blocks are indicated by abbreviations, where LOB, PAM, and MIX denote the LO buffer, power amplifier, and mixer, respectively.

All circuits are fully differential and run on a 3.3 V power supply. The SiGe technology employed for chip fabrication features HBTs with an f _T, an f _max, and a ring-oscillator gate delay τ_D of approximately 225 GHz, 320 GHz, and 2.7 ps, respectively. Fig. 2 shows microphotographs of the signal-generation chip and the dual–TRX chip with labeled building blocks. The die sizes are 728 × 728 µm² and 1028 × 1128 µm², respectively.

Fig. 2. (a) Microphotograph of the signal-generation chip. Size: 728 × 728 µm². (b) Microphotograph of the dual–TRX chip. The Rat-race (RR) coupler is indicated by an arrow. It surrounds the mixer and also connects the power amplifier. Size: 1028 × 1128 µm². (c) LOB (above) and PAM test chips with auxiliary baluns for single-ended characterization.

B) Dual-transceiver chip

The LO buffer in the TRX chip (cf. Figs 1 and 2) is based on the circuit shown in [Reference Wagner, Forstner, Haider, Stelzer and Jaeger10] and draws 25 mA. It was matched to a differential impedance of 70 Ω at the input and to 35 Ω at the output in order to allow connection of two 70 Ω transmission lines in parallel. The first LO buffer in the TRX circuitry compensates for losses due to interconnections, such as bond–wire transitions and tracks, and distributes the LO signal to the downstream TRX cells, where the LO buffers operate already in compression, that is, they work as limiters in order to supply the mixers with a constant LO drive. Fig. 3 (a) shows the measured single-ended S-parameters of the LO buffer test chip, which is shown in Fig. 2 (c). It uses LC-baluns at the input and output ports to perform the single-ended to differential conversion. Additionally, one branch of the buffer output was terminated by a resistor in order to employ the same baluns at the input and output. The desired center frequency of 125 GHz was achieved. Of course, the behavior of the buffer in this case was also influenced by the applied baluns used. Nevertheless, good matching in the target frequency range can be assumed. The peak small-signal gain was measured to be 12.7 dB, and the 3 dB bandwidth was 7.5 GHz. The insertion loss of the LC-baluns was 3 dB, measured using a back-to-back configuration. Considering this value, the de-embedded small-signal gain can be estimated to be 15.7 dB. The simulated saturated output power of the bare LO buffer is approximately 5 dBm.

Fig. 3. Measured S-parameters of (a) the LO buffer test chip and (b) the power amplifier test chip. Both results are not de-embedded from the input and output LC-baluns.

The downstream power amplifier in the TX path boosts the signal. It draws 32 mA and is based on a cascode topology. Designing a separate test chip by employing the above-mentioned LC-baluns was again required to allow characterization in a single-ended measurement environment (cf. Fig. 2 (c)). Fig. 3 (b) shows the measured S-parameters. The circuitry exhibits a well-matched behavior over the target frequency span, although the minimum return loss is a little off-center. A peak small-signal gain of 11.7 dB, which equals 14.7 dB when the losses of the baluns are taken into account, and a 3 dB bandwidth of 12.5 GHz were measured. The saturated output power was measured to be higher than 7 dBm. However, the value was obtained with a W-band power meter, which is not calibrated above 110 GHz, but its operation has been verified.

A Gilbert cell topology was employed in making the double-balanced mixer. The circuit as implemented makes use neither of resistive emitter degeneration nor of a tail current source. Thus, the circuit is very sensitive to variations in the biasing point of the differential pair. The biasing network uses a diode-connected transistor to set the bias voltage at the RF input transistors. However, the emitter length of the diode-connected transistor in the biasing network was chosen to be smaller than that in the differential pair. Since these two devices show different forward voltages, the biasing point changes and consequently the tail current increases significantly, which degrades the performance of the mixer in terms of gain and noise figure. Nevertheless, a gain of approximately 10 dB at 125 GHz was measured.

III. 122 GHz FRONTEND

Fig. 4 (a) shows a block diagram of the radar sensor. The direct-digital synthesizer (DDS), phase-frequency discriminator (PFD), and loop filter (LF) are not located at the frontend, instead they are incorporated in the baseband board. Fig. 4 (b) depicts the radar demonstrator frontend in chip-on-board technology, which was built on a printed circuit board with a layer stack according to [Reference Wagner, Feger, Stelzer, Haderer, Fischer and Jaeger11]. The design required low-loss interconnections because of the high operating frequency. Hence, bond–wire transitions and tracks for RF signals were kept as short as possible. To this end, the bare dies were attached in cavities in order to minimize the length of the bond–wires. Additionally, a differential off-chip bond–wire matching structure in conjunction with a differential single-patch antenna was designed for the TX and RX ports. The layout is shown in Fig. 4 (c) together with the chip arrangement. It uses a multisection transformer with two sections of transmission lines with lengths of approximately a quarter wavelength (λ/4) to overcome the high–impedance difference between the bond–wires and the antenna. The simulated insertion loss of the bond-wire transition including matching structure is 2.5 dB and the simulated differential single-patch microstrip antenna has a gain of approximately 6 dBi, a center frequency of 121 GHz, and a relative 10 dB return loss bandwidth of 7%.

Fig. 4. (a) Block diagram of the radar sensor. It features an offset-loop PLL and two cascaded TRX chips. The DDS, PFD, and LF are located at the baseband board. (b) 120 GHz quasi-monostatic radar frontend with two channels perpendicularly arranged similar to a polarimetric radar. Size: 4 × 3.5 cm². (c) Breakout of the PCB layout showing the chip arrangement with the multisection transformer bond–wire matching structures and the differential single-patch microstrip antennas.

The radar frontend (Figs. 4 (a) and (b)) uses a 17 GHz down-converter, a signal-generation chip, and two cascaded TRX chips forming a two-channel frontend. Obviously, each TRX uses the quasi-monostatic cells with separate TX and RX antennas. The output signal of the monostatic cell, however, was used for LO distribution, that is, it was connected to the LO input port of the downstream TRX chip. The perpendicular alignment of the TX and RX antennas allows TRX chips with different planes of polarization to be paired, thus forming a polarimetric radar. In this context, RX1/TX2 and TX1/RX2 can be combined. Other combinations allow measurement of the cross-polarization response of targets.

The signal-generation chip and the first TRX chip are collocated in a common cavity. Thus, the LO connection by means of chip-to-chip bonding was accomplished at the minimum distance. The LO connection between the TRX chips required distribution via tracks. However, the high gain of the LO buffer mitigates this constraint and ensures a proper LO level at the downstream TRX.

The 17 GHz SiGe down-converter chip is similar to that presented in [Reference Starzer, Wagner, Lukashevich, Forstner, Maurer and Stelzer12]. It allows conversion of the prescaler output, which is around 15 GHz, down to a frequency that can be processed by the phase-locked loop (PLL) synthesizer located on the baseband board. This configuration leads to an offset-loop configuration for VCO stabilization [Reference Wagner, Stelzer and Jaeger13]. Since the prescaler frequency is lower than the down-converter frequency, the tuning behavior is inverted and the control deviation decreases as the output frequency increases (reverse frequency position). Consequently, the polarity of the charge-pump current must be inverted for proper operation. For baseband signal generation and data acquisition, a fully customized base-band board similar to that described in [Reference Haderer, Wagner, Feger and Stelzer14] was employed.

IV. EXPERIMENTAL SETUP AND RESULTS

For the subsequent measurements, the PLL was equipped with a passive loop filter that does not allow generating tuning voltages exceeding the charge-pump supply voltage of 5 V. Hence, the maximum operating frequency in this setup was limited to approximately 123 GHz. The frequency sweep was accomplished by means of a DDS connected at the reference input of the 120 GHz PLL synthesizer. All measurement results presented are based on a single chirp measurement evaluated by applying a Von-Hann window function and subsequent Fourier transformation.

The first experimental setup is depicted in Fig. 5 (a). A small corner-cube (CC) reflector with a length of 39 mm at the shortest edge with a corresponding radar cross-section (RCS) of 1.9 dBsm served as target in the far field. The CC was attached on a wooden pole, which was again mounted on a linear rail in order to move the target back and forth. The FMCW sensor performed down chirps from f _start = 122 GHz to f _stop = 117 GHz within T _sweep = 2 ms, and N = 2500 data points were sampled per measurement cycle and channel. The measured amplitudes over distances from 1 to 4.5 m are shown in Fig. 5 (b). The figure also includes the predicted received signal amplitude. To this end, a link budget based on the basic radar equation (e. g., [Reference Skolnik15]) for point targets was calculated. Note that 5 dB IF amplifier gain were also incorporated.

Fig. 5. (a) First experimental setup with a small CC (1.9 dBsm) mounted on a linear rail. (b) Measured amplitude over target distance compared to the theoretical values according to the basic radar equation.

Both results are in close agreement and the graphs nearly cover each other. However, the simulated values had to be shifted by −3 dB to consider the performance loss of the TRX due to the thermal warming of the chips. The outlier at 4 m stems from an interference of the metallic body of the linear rail. The link budget calculation furthermore confirmed the 2.5 dB insertion loss of the bond–wire transition (cold TRX).

The second experimental setup is shown in Fig. 6 (a). Two static CCs, CC₁ = 9.4 dBsm and CC₂ = 12.1 dBsm, were placed at different distances and angles. The FMCW parameters for this measurement setup were set to f _start = 123 GHz, f _stop = 116 GHz, T _sweep = 3 ms, and N = 3750, that is, a sweep bandwidth of 7 GHz. Fig. 6 (b) depicts the resulting spectrum with two dominant peaks at 3.4 m (CC₁) and 4.0 m (CC₂). Another small peak at 4.5 m origins from the corner of the anechoic chamber.

Fig. 6. (a) Second experimental setup with two static CCs. (b) Measured amplitude spectrum. FMWC parameters: f _start = 123 GHz, f _stop = 116 GHz, and T _sweep = 3 ms.

To further evaluate the quality of the measurement results, 500 individual measurements were taken and statistically evaluated. Fig. 7 depicts the 500 measurement results for the position of CC₁ and shows the corresponding histogram with a binwidth of 45 µm. A Gaussian distribution of identical mean and variance was inserted additionally. The evaluation for the CC positions yielded means and standard deviations of μ_CC1 = 3432.598 mm, σ_CC1 = 115 µm and μ_CC2 = 4061.003 mm, σ_CC2 = 133 µm, respectively. The standard deviation at CC₂ is greater than that at CC₁ since the signal-to-noise ratio is slightly worse due to reflections of the metallic tripod and multipath effects in the vicinity to the corner. The Cramér–Rao bound states a limit below which the variance of an unbiased estimator can not fall [Reference Feger, Wagner, Schuster, Scheiblhofer, Jaeger and Stelzer16]. The results above attained this theoretical limit, which is also an indicator for a well–designed system.

Fig. 7. (a) 500 individual measurement results for position of CC₁. (b) Histogram of the 500 individual measurements (binwidth 45 µm) and Gaussian distribution with identical mean and variance.

As a final inspection, the corresponding windowing function (Von-Hann window) was plotted over the target peaks as can be seen in Fig. 8 (a). The close-up view for the peak of CC₁ is shown in Fig. 8 (b). The main lobes match very well and only a minor broadening can be examined in the measurement data. Thus, one can conclude that a proper linear frequency ramp with 7 GHz bandwidth can be provided by the PLL. Also chips, matching structure, and antenna provide sufficient bandwidth, because any inferior behavior would inevitably broaden the main lobe and hence affect the variance of the estimation results.

Fig. 8. (a) Comparison of the resulting measurement peaks with the simulated Von-Hann windowing function. (b) Close-up of peak CC₁. Only a minor minor broadening of the main lobe can be identified.