The technological means now exists for approaching the fundamental limiting scales of solid-state electronics in which a single electron can, in principle, represent a single bit in an information flow through a device or circuit. The burgeoning field of single-electron tunneling (SET) effects, although currently operating at very low temperatures, has brought this consideration into the forefront. Indeed, the recent observations of SET effects in poly-Si structures at room temperature by Yano et al. [1] has grabbed the attention of the semiconductor industry. While there remains considerable debate over whether the latter observations are really single-electron effects, the resulting behavior has important implications to future semiconductor electronics, regardless of the final interpretation of the physics involved.

We pointed out in Chapter 1 that the semiconductor industry is following a linear scaling law that is expected to be fairly rigorous, at least into the first decade of the next century. This relationship will lead to devices with critical dimensions well below 0.1 μm. Research devices have been made with drawn gate lengths down to 20 nm in GaAs and 40 nm in Si MOSFETs. This suggests that such devices can be expected to appear in integrated circuits within a few decades (by 2020 if scaling rules at that time are to be believed). However, it is clear from a variety of considerations that the devices themselves may well not be the limitation on continued growth in device density within the integrated circuit chip.