I. INTRODUCTION
Energy consumption of the wireless communication infrastructure has become a major concern, particularly when introducing bandwidth-optimized modulation schemes with high peak-to-average power ratios (PAPRs). Consequently, concepts for highly efficient power amplifiers have become the subject of intensive research. These efforts are presently focusing on switch-mode operation [Reference Hung, Rode, Larson and Asbeck1–Reference Milosovic, van der Tang and van Roermund3] as it inherently offers a higher power-added efficiency than the conventional analog classes. This is mainly because the losses associated with the saturated mode of operation (on- or off-states) can be very small.
One of the most advanced switch-mode amplifier concepts is the class-S approach [Reference Iwamoto4–Reference Wentzel, Meliani and Heinrich8, 14]: a given analog signal is converted to a 1-bit digital bit stream using a band-pass delta-sigma modulator (BPDSM) [Reference Ersoy, Meliani, Khalil and Heinrich9]. The digital signal is then amplified using a highly efficient power switch. An analog band-pass filter at the output of these switching stages reconstructs the amplified signal at the signal frequency f 0. For ideal devices, the class-S concept avoids any overlap of output voltage and current in time and yields high efficiency, independently of the power back-off. Therefore, it is very popular at audio frequencies [Reference Iwamoto4, Reference Sommarek, Saari, Lindeberg, Vankka and Halonen10].
However, this concept needs very fast and broadband power transistors and thus it is less explored at higher frequencies. Only a few realization examples of class-S amplifiers in the microwave frequency range have been presented so far [Reference Meliani, Flucke, Wentzel, Würfl, Heinrich and Tränkle5–Reference Wentzel, Meliani and Heinrich8]. Most of these realizations of class-S amplifiers are employing the current-mode topology [Reference Meliani6–Reference Wentzel, Meliani and Heinrich8], whereas best results for voltage-mode yield peak output powers well below 1 W only (21 dBm at 62% efficiency [Reference Hung, Rode, Larson and Asbeck1]). This is because the driver circuits in the current-mode version are more simple (both transistor sources are connected to ground), the output capacitances play a less important role, and the load impedance for a given transistor is higher.
In this paper, we report on results of the voltage-mode version of such an amplifier, presenting a 450 MHz class-S amplifier in GaN technology. Although this configuration has the above-mentioned drawbacks compared to the current-mode, it also offers important advantages compared to current mode:
– A simple voltage supply is needed instead of a more complicated and less efficient DC constant-current source.
– Loss mechanisms are dominated by output capacitances and not by current, which offers additional degrees of freedom for optimization.
– The output of the switching stage is single ended with a simple series resonator, thus one avoids the balun required for current-mode circuits, which reduces losses and complexity of the output network.
GaN is chosen as semiconductor technology for this purpose as it combines high breakdown voltage and low output capacitance for a given current with high speed.
The paper is organized as follows: Sections II and III give an overview on the voltage-mode class-S concept and the realized class-S amplifier, respectively. Section IV presents the measurement data and Section V the analysis of the loss mechanisms. Finally, Section VI discusses the results and the consequences with regard to further improvements.
II. THE VOLTAGE-MODE CLASS-S CONCEPT
Figure 1 illustrates the concept of the voltage-mode class-S amplifier and presents its main components along with the time-domain wave forms at different points. The input of the power switching stage (MMIC – monolithic microwave integrated circuit) is fed differentially with a band-pass delta-sigma (BPDS)-modulated digital signal. This bit sequence is non-periodic and was converted from an analog signal in the band around frequency f 0 (which can be code division multiple access (CDMA), wideband CDMA (WCDMA), orthogonal frequency-division multiplexing (OFDM), or a common harmonic sinusoidal signal). The sampling frequency typically is four times higher than the signal frequency f 0. But, depending on the modulation, this carrier oversampling ratio can be varied. The BPDS bit sequence is then amplified by means of an MMIC switching stage (T 1 and T 2) in push–pull configuration, switching the output voltage on and off between the +V DD and 0 V.
Fig. 1. Concept of the voltage-mode class-S amplifier.
The freewheeling diodes D 1 and D 2 in Fig. 1 are required to protect the final stage GaN–HEMTs against backward currents from the filter, which occur under class-S operation with BPDS input signals. The challenge in realizing such diodes is to combine high breakdown voltage (70 V) with high forward currents (2 A) and high switching speeds (up to 2 Gbps). Hence, we could not use commercially available components but had to employ special high-power GaAs Schottky diodes fabricated in-house, using a dedicated high-voltage InGaP/GaAs-HBT process (see [Reference Kurpas, Wentzel, Janke, Meliani, Heinrich and Würfl11]).
The L-C filter at the output of the final stage acts as a series resonator and has to reconstruct the wanted signal from the bit sequence. It forces the output current I F to be sinusoidal, whereas output-voltage waveform remains rectangular. This means, in the ideal case, all spectral components except for f 0 see an infinitely high output impedance.
III. THE REALIZED VOLTAGE-MODE CLASS-S AMPLIFIER
A) The MMIC power switching stage
The power switching stage for the amplification of the BPDS bit sequences is fabricated on-chip using the FBH GaN–HEMT process. The circuit diagram of the power-switch MMIC is shown in Fig. 2.
Fig. 2. Circuit diagram of the GaN–HEMT MMIC power-switching stage.
The final stage of the voltage-mode switching amplifier consists of two transistors (T 1, T 2) in push–pull configuration with 4 × 250 µm gate width each. Circuit design including large signal time-domain simulations was performed using the Chalmers (Angelov) transistor model, modified for application to AlGaN/GaN HEMTs on SiC in the time domain [Reference Angelov, Desmaris, Dynefors, Nilsson, Rorsman and Zirath12].
The driver stage consists of two parts, 1 and 2: a common-source amplifier (1) with a passive load (R 1) of around 20 Ω and a differential amplifier (2) with the passive loads R 2 and R 3. Note that all the driver impedances (R 1–R 3) have to be realized broadband, which makes it impossible to apply classical reactive impedance matching.
The common-source configuration (1) amplifies the single-ended BPDS input signal (small amplitude: ≈1.8V pp) and feeds one input of the differential amplifier (T D2). The second input (T D3) is RF-grounded, thus. Moreover, the connected sources of T D2 and T D3 are fed symmetrically with a constant current through R 4.
The differential amplifier generates the input voltages V in1 and V in2 for the final stage. The signal at the gate of the upper transistor T 1 ranges between a voltage lower than the pinch-off voltage V P (typically −4 V) and V DD (in our case: 50 V). Thus, a very high input voltage swing (−10 V ≤ V in1 ≤ 50 V) is present at the gate of T 1. A comparatively small voltage swing needs to be generated at the input of T 2 (−10 V ≤ V in2 ≤ 1 V). Here, 1 V is enough to put T 2 in the “on-state.”
Usually, we connect the source of transistor T 2 directly to ground. But this connection is realized off-chip. So, we have an additional degree of freedom in biasing the source of the lower final stage transistor.
Measured switch efficiencies for an output load of 50 Ω were around 80% at 1.8 Gbps for the maximum drain supply voltage V DD of 50 V. This value refers to the efficiency of the power switch alone, i.e., it is calculated as the ratio between broadband output power of the digital signal at a 50 Ω load and DC power consumption. This quantity characterizes the quality of the power switch and hence is an important figure of merit. An output power of 8 W was reached for typical BPDS or PRBS signals at V DD at T 1. Figure 3 shows a chip photograph of the MMIC.
Fig. 3. Chip photo of the GaN power-switch MMIC including common-source and differential driver circuit; chip area: 2.8 × 1.9 mm2.
B) Filter and realized amplifier
The output network of the voltage-mode class-S amplifier must provide two functions, reconstructing the output signal (band-pass filter) and transforming the 50 Ω (Z L) output load to the optimum load Z OPT of the final stage of the MMIC (see Fig. 2). Reconstruction means filtering out of the 1.8 Gbps digital bit stream the narrowband signal around the frequency f 0 of 450 MHz, with very low losses in order to not degrade efficiency.
The output network was designed with two L-C parts in series for the band-pass filtering and a simple L-C low-pass network for the matching to 50 Ω. The optimum output impedance (Z OPT) is around 40 Ω for the used final stage configuration with two 4 × 250 µm GaN–HEMTs. Figure 4 shows the output network realized.
Fig. 4. Circuit of the realized output network including band-pass filtering and matching to 50 Ω.
The complete network was fabricated on RO 4003 PCB laminate (εr = 3.55) with 0.81 mm substrate thickness and a conductor thickness of 70 µm. It was mounted on a copper heat sink. To minimize parasitic capacitances of the interconnections, backside metallization was removed under the band-pass filter structure. The chips are mounted on the heat sink and connected to the board by wire bonding.
In addition to the circuit simulations of the filter, we performed EM simulations to account for all layout parasitics. The simulated overall insertion loss of the output network is about 0.8 dB. Accurate measurements of the filter could not be performed because of calibration problems due to the different interconnect types, on-wafer at the input (for the bond-wire connection to the hybrid board), and sub miniature version A (SMA) at the output. Figure 5 presents the realized amplifier.
Fig. 5. The complete class-S amplifier including GaN power-switch MMIC, flip-chip mounted GaAs Schottky-diodes and hybrid output network (filter and matching); zoom: GaN MMIC and GaAs diodes.
IV. MEASUREMENTS
A) Class-S: peak power
All class-S measurements were performed by feeding the GaN MMIC single ended with a 1.6 Gbps BPDS bit sequence [Reference Ersoy, Meliani, Khalil and Heinrich9] and an encoded single-tone signal of 400 MHz. The bit sequence was generated using Matlab and loaded into a bit pattern generator.
First, a bit pattern corresponding to the highest stable output signal of the BPDSM was applied (referred to as “0 dB back-off” in the following). For this bit stream, the drain supply voltage V DD at the final stage was varied. In Fig. 6, the measured output power at the 400 MHz signal frequency and the corresponding efficiencies are plotted as a function of the DC voltage V DD.
Fig. 6. Measured output power (P out) and efficiency of the voltage-mode class-S amplifier as a function of the drain supply voltage V DD (class-S operation at BPDS stability limit, i.e., 0 dB back-off).
The voltage-mode class-S amplifier reaches a maximum output power of 3.4 W (4 × 250 µm final stage power switches) at a (drain) efficiency of 38%. A peak efficiency of 52% is achieved at an output power of 0.5 W. These are record values in terms of power and efficiency for this class-S configuration in 450 MHz band using classical BPDSM. On the other hand, they are still lower than those reached by other concepts such as Doherty and class-F. Hence, the reasons need to be discussed, which is done below in Sections IVC and V.
The drop in efficiency with increasing drain-supply voltage and output power is related to the transistor technology (breakdown voltage around 60 V). One can expect to see an improved behavior when further optimizing technology.
In order to evaluate the characteristics of the class-S amplifier in more depth, it is important to have a look at the spectrum. Figure 7 presents the corresponding data for input and output of the amplifier.
Fig. 7. (a,b) Input and output BPDS spectra of the realized voltage-mode class-S amplifier for a BPDS bit sequence with 0 dB power back-off. (a) Input spectrum (7 dBm at 400 MHz). (b) Output spectrum (34.5 dBm at 400 MHz; V DD = 40 V)
At the input (see Fig. 7a) we observe the typical noise notch of the BPDS-modulated signal. The signal-to-noise ratio (SNR) in the frequency band around 400 MHz (i.e. in the notch) is more than 60 dB and almost 30 dB out of band. The output spectrum (Fig. 7b) exhibits an SNR of nearly 45 dB inside the notch around the signal frequency f 0 (drain supply voltage is 40 V and output power 34.5 dBm). This demonstrates the functionality of the class-S amplifier. The loss in SNR of about 15 dB indicates the level of nonlinearities contributed by the amplifier. Out of band one observes the influence of the band-pass filter at the output with a noise suppression of more than 35 dB. Furthermore, the amplifier shows a high power gain of about 28 dB at 400 MHz.
B) Class-S: power back-off
The behavior at power back-off is an important aspect since a transmitter is usually operated at an average power below the peak power. This PAPR is particularly large for advanced modulation schemes such as OFDM. Figure 8 presents the corresponding results studying output power and efficiency versus the power back-off. This was performed by applying different bit streams with varying encoded signal power, from 0 dB (peak power) down to 10 dB back-off, i.e., a 10 dB lower power. A drain supply voltage V DD of 40 V at the final stage was applied. The 0 dB power back-off case corresponds to the highest output power where the used fourth-order BPDSM still operates in a stable regime and corresponds to the peak power case considered in the previous subsection.
Fig. 8. Measured output power (P out) and efficiency of the realized voltage-mode class-S amplifier vs. power back-off (V DD = 40 V).
Efficiency decreases from 49 to 6% when reducing signal power from 0 dB down to 10 dB back-off. For the usual universal mobile telecommunication system (UMTS) value of the PAPR of 6 dB, the amplifier achieves an efficiency of about 15%. This degradation from 49% down to 15% is lower than for a conventional class-AB amplifier, but still relatively high given that the ideal lossless class-S power amplifier (PA) does not show any degradation at all. Comparing the results to those of the previously realized current-mode class-S PA (36 to 9% for 10 dB back-off) [Reference Wentzel, Meliani and Heinrich8], one has to note that the voltage-mode version achieves higher efficiencies for peak power, but the decrease with back-off is even more pronounced than for the current-mode case. Thus, the influence of the loss mechanisms in the voltage mode, e.g., the parasitic capacitances, needs to be considered in more detail, which is done in Section V.
To illustrate the effect of different input power levels at the signal frequency f 0 (back-off operation) along the building blocks of the voltage-mode class-S PA, Fig. 9 shows qualitative time-domain waveforms for two single-tone signals with 0 dB (full-scale) and 10 dB power back-off encoded.
Fig. 9. Concept of the voltage-mode class-S amplifier with signals for full scale and 10 dB back-off shown at the terminals of BPDSM, final stage transistors and reconstruction filter.
The analog signals are converted by a BPDSM into digital ones having an amplitude difference of 10 dB at the signal frequency f 0 encoded. This leads to 10 dB less output power for the proper back-off input signal assuming no additional parasitic effects. The maximum amplitudes of the BPDS bit sequences are equal (+V DD at output of final stage – see Fig. 9), but the mean value is different along with the back-off encoded. Thus, the current I L (cf. Fig. 9) in the load differs and so the output power in the full-scale case should be 10 dB higher than with a 10 dB back-off input signal.
C) Influence of coding efficiency
One possibility to improve efficiency is to modify the digital input signal, i.e., to change the modulation scheme. In order to explain this in more detail let us consider the BPDS modulator. We define the maximum signal amplitude at the input of the BPDSM to be A s and the amplitude of the modulated digital signal to A digital. The ratio A s/A digital will be referred to as amplitude coding efficiency (ACE) in the following (ACE is closely related to the power-based coding efficiency definition). The key issue here is the question of which maximum A s can be encoded in a digital signal of amplitude A digital. A fourth-order BPDSM with an over-sampling ratio of 4 yields only ACE values around 0.8 under stable operation. The extreme case in this regard is the square-wave signal, which reaches ACE = 4/π = 1.3, i.e., almost double the BPDS value. This is basically the class-D situation, where the amplitude of the signal is constant. Therefore, in order to determine the potential of our amplifier and to benchmark it against class-D, we measured it again, now replacing the BPDS bit sequence at the input by a square-wave signal at 400 MHz. Figure 10 presents the new data and compares them with the BPDS class-S results of Fig. 6.
Fig. 10. Measured output power (P out) and efficiency against supply voltage V DD for BPDS and sqw operation.
In the square-wave case (sqw), for a maximum possible V DD = 48 V (because of drain current I D limitations), a maximum output power of 7 W is achieved with an efficiency of 64%, and for output powers up to 2.3 W efficiencies beyond 70% are reached.
This shows that coding efficiency plays a major role in optimizing the class-S amplifier power characteristics. A considerable part of the losses occur in the transistor as switching losses effected by drain–source capacitance (C DS) in parallel with the capacitance of the diodes. They depend on voltage, i.e., on the amplitude V DD of the digital signal. For a given V DD and thus a fixed amount of these losses, the BPDS case delivers a signal amplitude at 400 MHz around 0.8V DD only whereas the sqw yields (4/π)V DD, thus significantly improving efficiency.
V. DISCUSSION OF LOSS MECHANISMS
To clarify the influence of the different loss mechanisms present in the voltage-mode class-S operation, we performed simulations of the realized structure for 0.5 (modulator operation in stable region), 5.5, and 10 dB PAPR. For the transistors we employed a simplified switch-based model including the major intrinsic elements such as R dson, R dsoff, C ds, C gd, C gs, and R i (see [Reference Wentzel, Schnieder, Meliani and Heinrich13]). This provides a better control of the relevant quantities under switch-mode operation than the full nonlinear description and yet yields good accuracy. A drain supply voltage of 40 V at the final stage was chosen, which is in a realistic range regarding P out and efficiency and, on the other hand, avoids model inaccuracies associated with the breakdown voltage V br of the transistors.
Starting from the case with all losses and parasitics included, we reduced step by step one of the different non-ideal effects (R dson, C diode, C ds, filter losses, C gd, and R diode) while keeping all other elements at their realistic value. This is to determine the influence of each parasitic effect on overall efficiency. The following cases are studied:
– The on-resistances of the switching transistors R dson are reduced from their actual value of 5.5 Ω to a nearly ideal value of 1 mΩ.
– The diode parallel capacitance C diode and the drain–source capacitance of the final stage transistors C ds are reduced from 2.8 and 0.3 pF, respectively, to a negligible value of 1 fF.
– The filter losses are minimized by realizing it in the simulation with ideal elements from the ADS library having an infinite bandwidth and no ohmic losses.
– The drain–gate capacitance C gd of the transistor is reduced from 0.15 pF to 1 fF.
– The forward resistance of the diodes R diode is reduced from the actual value of 3.2 Ω down to 1 mΩ.
Table 1 presents the results listing output power (P out) at the signal frequency, the consumed DC power (P dc), and the (drain) efficiency (ηdrain) as a function of the power back-off. The order reflects the impact on efficiency. The respective improvement can be seen from the right-most column.
Table 1. Simulated output characteristics (output power, consumed DC power, (drain) efficiency, and corresponding efficiency improvement) of the realized voltage-mode class-S amplifier as a function of the power back-off when reducing the different parasitics; V DD = 40 V.
If all parasitics are accounted for, the simulations for all power back-offs (0.5, 5.5, and 10 dB) yield a good agreement with the measurements. For example, at a PAPR of 0.5 dB, the simulation shows an output power at the signal frequency of 2.44 W at around 47% efficiency, which is very close to the measured values (2.47 W and 45%, see Fig. 8 for V DD = 40 V). This confirms the validity of our models and the simulations.
Discussing the results of Table 1, one first has to state that there is not a single effect dominating the loss behavior. The on-resistance of the transistor R dson has the strongest influence, which could not be expected, because a voltage is switched. But because its value of 5.5 Ω is relatively large compared to the load impedance it causes high ohmic losses. This is partly due to the fact that the voltage-mode version needs a load resistance of only one-quarter of the corresponding current-mode counterpart. As expected the influence of R dson decreases with back-off (due to the lower load current). Increasing the supply voltage assuming the same R dson would improve the situation but is demanding on the transistor technology side.
The second-important effect is due to the parasitic capacitances C diode and C ds of the diodes and transistors, respectively, whose reduction would result in efficiency improvements between 7% (0.5 dB PAPR) and 3% (10 dB PAPR), depending on the back-off level. These are the loss mechanisms one expects for the voltage-mode type. During operation, C ds of the off-state transistor in parallel with C diode is charged with V DD and short circuited if the transistor switches to the on-state. Consequently, the charged energy is lost in each switch event. Thus, the lower the parasitic capacitance, the lower the consumed DC power. This effect does not depend on output power and thus increases with rising PAPR.
The loss associated with the hybrid output network is less significant than that due to R dson and the output capacitances discussed before. The degradation in efficiency closely corresponds to the 0.8 dB insertion loss, and thus removing the filter losses leads to a higher P out. Furthermore, we found that, despite of its small value of 150 fF, the influence of the gate–drain capacitance C gd of the switching transistors cannot be neglected. One should note that varying this parameter does not affect output power but only changes the DC power required, for all PAPR levels. The resistance R diode does not significantly change efficiency as it shows almost no influence in the simulation.
Finally, Fig. 11 illustrates the efficiency (ηdrain) improvements when eliminating the different each parasitic effects (R dson, C diode, C ds, filter losses, C gd, and R diode) as a function of the power back-off in a bar chart.
Fig. 11. Simulated efficiency (ηdrain) improvement of the voltage-mode class-S amplifier for 0.5 dB (stable BPDSM), 5.5 and 10 dB power back-off when reducing the different parasitics; V DD = 40 V.
Summarizing, reducing the parasitics introduced by the diode appears to be the first step to go (e.g., carefully checking the current capabilities needed since they determine diode size and thus capacitance). Improving R dson (or increasing breakdown voltage while keeping R dson constant) is more difficult since it requires optimizations in GaN transistor technology. Work along these lines is ongoing.
VI. CONCLUSION
A novel voltage-mode class-S amplifier including a complex three-stage GaN power switch MMIC, two GaAs Schottky diodes, and a lumped hybrid output network (filter and matching) was realized as a compact hybrid module for the 450 MHz band. This is the first published voltage-mode class-S realization for the power range well above 1 W in this frequency range.
Using a single-tone BPDS bit sequence, a peak efficiency of 52% at 400 MHz with an output power of 0.5 W and a maximum output power of 3.4 W with 38% efficiency were achieved. Lowering the input power level by 10 dB, efficiency drops from 49% (0 dB back-off) to 6% (10 dB PAPR). This performance is not overwhelming in terms of absolute numbers, the results are comparable with current-mode realizations [Reference Meliani6, Reference Wentzel, Meliani and Heinrich8].
On the hardware side, we identify as main reasons for efficiency degradation the on-resistance of the transistors, the parasitic capacitance of the diodes (C diode), and the drain–source capacitance C ds of the transistors.
However, one can improve performance also without changing the hardware. One is to increase coding efficiency of the modulation. We have shown this using measurements with square-wave excitation, equivalent to class-D. This case stands for a modulation with high coding efficiency. The amplitude coding efficiency reaches 1.3 while the standard BPDS modulations remain around 0.8. This leads to significant improvements: output power goes up to 7 W from 3.4 W for BPDSM, and corresponding efficiency reaches 64% (compared to 38% for BPDSM). Consequently, the development of modulation schemes with higher coding efficiencies is crucial for further class-S developments at microwave frequencies.
The results obtained are to the authors’ knowledge the best ever presented for voltage-mode class-S microwave amplifier and clarify the potential of this concept. Moreover, the class-D data compare very favorable with pure class-D voltage-mode amplifiers in this frequency range so far and demonstrate that GaN-based circuits allow to push the frequency limits of voltage-mode class-D PAs into the microwave range.
Andreas Wentzel received the Dipl.-Ing. degree in electrical engineering from the Technical University of Berlin, Germany, in 2006 and is currently a Ph.D. candidate in the microwave department of the Ferdinand-Braun-Institut (FBH) in Berlin, Germany. His main research interests are design and optimization of switch-mode power amplifiers, especially in class-S and class-D operation, as well as time-domain measurement techniques and modeling.
Chafik Meliani received his M.S. degree in microelectronics and Ph.D. in high-frequency electronics from the University of Denis Diderot, Paris, in 1999 and 2003, respectively. From 1999 to 2003 he worked with FranceTelecom R&D and Alcatel in Paris, France, on the design of low noise amplifiers, high bit rate circuits, and modules beyond 40 Gbps. He joined the Ferdinand-Braun-Institut für Höchstfrequenztechnik (FBH), Berlin, Germany in 2003, where he is currently a Senior Scientist. His research interests are high bit rate circuits, power amplifiers, and HF front-end dedicated ICs.
Wolfgang Heinrich received the Dipl.-Ing., Dr.-Ing., and habilitation degrees in 1982, 1987, and 1992, respectively, all from the Technical University of Darmstadt, Germany. Since 1993, he has been with the Ferdinand-Braun-Institut (FBH) at Berlin, where he is head of the microwave department and deputy director of the institute. Since 2008, he is also professor at the Technical University of Berlin. His present research activities focus on MMIC design with emphasis on GaN power amplifiers, mm-wave packaging, and electromagnetic simulation. Prof. Heinrich has authored or coauthored more than 200 publications and conference contributions. He served as IEEE Distinguished Microwave Lecturer for the term 2003/2005 and was Associate Editor of the IEEE Transactions on MTT from 2008 to 2010. He was General Chair of the 2007 European Microwave Week in Munich, Germany. Since January 2010, he is a President of the European Microwave Association (EuMA).
