Introduction
In recent times, electronic warfare and navigation technology have changed rapidly. This change in technology requires highly precise and stable high frequency systems. It is well known that a frequency source is one of the critical subsystems of a radar system. Requirements of any radar system performance in terms of increased dynamic range, target detection sensitivity, and operational flexibility necessitate the achievement of improved spectral purity of carrier signal for transmitter and local oscillator signal for receiver. The performance of the frequency source needs to be maintained under all environmental stress screening such as vibration, shock, acceleration, high and low temperature, thermal shock and humidity, and so on. Efforts have been made in past to provide solutions, while the existing system and/or techniques include complex and sophisticated feedback mechanism based on electronic compensation methods. Therefore, there is a need of compact and non-complex techniques and methods for noise reduction in reference crystal based frequency source that operates in space constraint applications. Phase noise is defined as a random phase modulation of fundamental system generated signal. Random frequency pickups play an important role in noise performance of the system. In order to build a system with low vibration sensitivity, proper selection of essential components, electronic and mechanical stabilization techniques are preferred. Abundant literature is available on frequency systems based on phase-locked loop (PLL) design and development techniques for synthesis but its stabilization is a challenging task especially under random vibration (RV) environment of high g value. Electronic system that finds use in electronic warfare application has to face intense vibration condition, which necessities its performance stabilization. Phase noise performance of high precision frequency system is most important for their operation in such conditions. Phase noise of PLL-based frequency system is dependent on reference crystal [temperature compensated crystal oscillator (TCXO) or oven compensated crystal oscillator (OCXO)] induced phase-modulated noise which becomes excessively large at higher frequencies. Reference crystal generally composed of piezoelectric material (acceleration sensitive element) and its output signal purity is sensitive to lattice disturbance occurring due to vibration at closer frequency offset. Hence, for meeting phase noise requirements of PLL-based high precision system (e.g. unmanned aerial vehicle, helicopter, missiles, and other dynamic platforms), reference crystal stabilization is a must for acting clock for PLL. High precision frequency source with good phase noise performance also helps in processing of targets with lower Doppler frequency. Fig. 1(a) shows the basic block diagram of such PLL-based frequency synthesis system using reference crystal of 100 MHz as external clock which governs system phase noise performance [Reference Filler1, Reference Hati, Nelson and Howe2].
PLL is an electronic feedback system used to control output of voltage-controlled oscillator (VCO) that is responsible for specific frequency generation. The Slave oscillator's output phase can be controlled within the bandwidth (BW) of the PLL loop filter. High frequency radar and EW systems generally operate in X and Ku bands. Direct generation of precise frequency signal in high frequency X and Ku bands is difficult using PLL design technique due to high sensitivity of the VCO. Switching time is one of critical parameter in any frequency synthesizer system. Meeting the stringent requirement of 100 μs switching time in frequency hopping mode is difficult to achieve using integrated VCO PLL approach in X-band. Hence to overcome this difficulty, alternative approach to generate X-band signal using frequency multiplier IC along with S-band PLL is adopted. Active loop filter is used to generate higher tuning voltage to cover the entire band of operation of low sensitive VCO which will have a better phase noise characteristic. Indirect technique of X-band frequency generation has been employed by multiplying S-band PLL signal as shown in Fig. 1(b). Spurious (undesired frequency pickup) plays critical role in phase noise performance of such system. Occurrence of spurious due to reference crystal (i.e. TCXO, OCXO) are known as reference spurious, while spurious coming from remaining components comes under non-reference spurious. The effect of spurious can be reduced by proper selection of essential components in the initial stage of designing as per system requirements. The present disclosure provides methods for reduction of vibration induced noise on a reference crystal based frequency source.
The section “Performance analysis of PLL” explains noise sources in PLL and their contribution in phase noise and performance analysis of S-band PLL. The section “Effects of RV” explains the effects of RV on phase noise performance of reference crystals. The section “Stabilization techniques under RV” explains in-depth analysis of compensation techniques and stabilization mechanisms for g-sensitive reference crystal to improve the phase noise performance of PLL system. The section “Precautions” explains the preventive measures that have to be employed before and during RV test. The final section “Performance results” explains phase noise measurements before and after implementation of suggested techniques and stabilization mechanisms.
Performance analysis of PLL
Reference crystal (i.e. TCXO or OCXO) is a piezoelectric material which is prone to physical disturbance. Reference crystal acts as clock for phase frequency detector (PFD) of PLL. Phase noise degradation of reference crystal has direct impact on PLL output. Hence, stabilization of reference crystal under intense vibration environment is essential for maintaining phase noise performance. Loop filter design also play a critical role in determining the final output phase noise. Selection of type (i.e. passive or active) and order of loop filter is based on requirement and limitation.
Fundamental of PLL passive loop filter
The second-order filter is the preferred approach in the design of passive loop filter which provides lower resistance and higher capacitance value near the VCO with better reference spurious removal. In addition, RC low pass filtering stage can be added to reduce the excess. Loop filter having narrow BW is good at the expense of high lock time. Higher order loop filters with narrow loop BW approach is most effective in reducing spurious which leads to improvement in phase noise of PLL.
Fundamental of PLL active loop filter
When charge pump generated by passive PLL is not sufficient enough to drive VCO, then we prefer active PLL approach. It is having disadvantage of added in-band phase noise which is added by the op-amp used. It is generally recommended to have at least third-order loop filter in which added extra pole reduces additional flicker noise of the active device. One such scheme of implementation of active loop filter is shown in Fig. 2 [Reference Banerjee3–Reference Kosinski and Ballato5].
Use of higher order loop filter has advantage in case PFD frequency of PLL is larger than loop filter BW. Fig. 3 shows phase noise performance, locking time, and gain of active S-band PLL output. Making use of multiplier IC's for transforming lower frequency PLL signal to high frequency helps in lowering phase noise degradation factor as compared to direct generation. In present S-band PLL design, VCO phase noise is dominant outside the loop BW as seen in Figs 3(a) and 3(f). The voltage requirement (V tune) of VCO for frequency generation is shown in Fig. 3(b). Estimation of close loop BW of PLL along with the gain of the active loop filter is shown in Fig. 3(e). Reference phase noise which is dominant within the loop BW of the PLL is shown in Fig. 3(c). The VCO sensitivity which can be seen as constant for the V tune voltage range is shown in Fig. 3(d). The combined effect of the phase noise for the PLL is shown in Fig. 3(f). The second-order response of the system which shows system stability at the lock frequency 2.66 GHz is shown in Fig. 3(g). Close look can be taken for the frequency lock in Fig. 3(h) which takes 50 μs lock time.
Phase noise performance degrades 20log times the ratio of translated frequency to reference crystal as shown in equations (1) and (2).
Here, M is the multiplication factor with respect to reference crystal frequency.
Effects of RV
Vibration causes lattice disturbance in piezoelectric material components that causes phase fluctuations. In general, this effect is more prominent in higher-frequency oscillators due to increased signal phase sensitivity to mechanical deformation and decreased resonator quality factor. If these phase fluctuations are inside the oscillator feedback loop, they get converted as frequency fluctuations via Leeson effect within the resonator's half-BW. Reference crystal sensitivity to vibration is traditionally characterized by acceleration/vibration sensitivity, which is normalized frequency change per unit g, due to which resonant frequency shifts. The frequency shift (Δf) over the time is proportional to the magnitude of the time-dependent acceleration and depends on the direction of acceleration. In RV test, amplitude of vibration level is defined in terms of power spectral density (PSD). Level shift of phase noise (L(f v)) at particular offset from fundamental carrier frequency is shown in equation (3).
Here, peak g-sensitivity is A peak = $\sqrt {2 \times PSD}$ where $\bar{\Gamma }$ is acceleration sensitivity, f o is the fundamental frequency of reference crystal, and f v is the offset from fundamental frequency [4–Reference Tustin8].
$\bar{\Gamma }$ of any reference crystal used in PLL is dependent on PSD and vibration spectrum. It is defined in equation (4).
Selection of reference crystal depends on stability and its g-sensitivity which governs the phase noise characteristic under vibration. Spectrum of RV is known as PSD [${{g^2} \over {Hz}}$] which is critical while selecting the reference crystal as shown in Fig. 4. PSD curve governs intensity of vibrations induced during RV testing. PSD in vibrational testing has direct effect on phase noise amplification as it has impact on the piezo electric property of reference oscillator. Phase noise performance of typical reference crystal is shown in Fig. 5. Acceleration sensitivity of reference crystal of PLL system is also dependent of material axial behavior and is measured in [ppb/g] as shown in Fig. 6. Hence, mounting position of frequency determining components is axial dependent for effective stabilization mechanism.
Hence phase noise performance in different axis gets affected in different ways which needs to be taken care while selecting reference crystal.
Stabilization techniques under RV
Phase noise of PLL-based frequency synthesizer system is direct dependent on reference crystal phase noise. Reduction in g-sensitivity of reference crystal performance is important for system. g-sensitivity reduction is achieved in two ways in present article, i.e. reference oscillator spatial location and stabilization techniques. Finest spatial location (center of gravity) for mounting reference crystal is determined through structural analysis method. Mechanical and electrical [Reference Tustin8, Reference Lakshminarayanan9] stabilization techniques are used in this design to achieve improved phase noise performance under vibration.
Structural analysis
Structural analysis needs to be carried out for mounting of reference crystal at center of gravity and filtering out unit under test (UUT) resonance from PSD spectrum. This helps avoiding magnification of UUT resonance pickups during test as shown in Fig. 7. In present analysis as shown in Fig. 7, mechanical enclosure of UUT has self-resonance at 1.4 kHz. Hence, it needs modifications (i.e. positional weight analysis, physical profile alteration) in present design to filter out self-resonance from RV spectrum.
Stabilization of reference source
Mechanical stabilization
Vibration isolators or dampers are a special class of silicone rubber made of high mechanical properties rubbers with high damping in order to reach Q factor at resonance lower than 3. Vibration isolators are in use to isolate reference crystal module to avoid direct contact with UUT. It provides free floating, stress less assembly for reference crystal module which experiences lesser level of vibration than direct fixing arrangement. Such reference crystal assembly arrangement is shown in Fig. 8. Vibration isolator selection is critical as these are profile-dependent special class of rubber also making sure it qualifies environmental test requirements, i.e. temperature, shock, acceleration, humidity, and so on. To measure the effective performance improvement using vibration isolators, specialized sensors are used. Specialized sensors are class of high precision accelerometers which can even sense minor changes in magnitude of applied force. Significant improvement in reduction in intensity level (PSD) or damping effect by mechanically stabilizing to access of RV on reference crystal is shown in Fig. 9 [Reference Li and Das10–Reference Walls13].
Electrical stabilization
Electrical stabilization can be achieved by taking below mentioned point into consideration during design. These are combination of best practices followed while PBC design and lesson learnt (from electrical issues) during environmental testing of developed system.
• Decoupling capacitors on power supply voltage to each IC's and charge pump supply lines as these are most vulnerable to noise. Use of tantalum capacitors of different values (10 μF, 1 μF, 0.1 μF, 100 pF, and 1 kpF) at supply to reference crystal is must.
• Electrolytic capacitor in UUT main power supply for filtering external noise.
• Use of DC–DC converters with proper decoupling capacitors and make sure that their switching frequencies are not falling within PSD spectrum.
• Use of low noise voltage regulators for improved phase noise performance. Check their ripples are not within PSD spectrum.
• Protect charge pump line and VCO tuning voltage line of PLL from noisy signals by making trace length shorter (max 6 mm) and routing close to PLL chip.
• Isolated routing of reference signal to PLL using shielded co-axial cable to avoid conducted and radiated pickups.
• Avoid effect of acoustic noise and external vibration in the test chamber.
• Avoid any strain in RF and power supply cables during test.
• Use of shielded power connectors for UUT for avoiding external electromagnetic interference.
• Minimize the ground loops are of utmost importance for accurate measurements. Ground loops may interact with magnetic and electric field generated by the vibrating actuator and degrades the performance [Reference Hati, Nelson and Howe2].
All design aspects listed here are implemented while doing electrical design of PCB's and interconnections between them within the system. Assembly quality and workmanship also play important role in reducing vibration sensitivity of any system. Implementing all techniques and methods as per present disclosure reduces overall system vibrational sensitivity.
Precautions
Vibration fixture
Vibration fixtures are specially designed as per the mechanical profile of UUT. It must transfer uniform vibration effect on UUT and needs to be monitored using vibration sensors mounted on fixtures.
Sensor mounting
Use good quality sensor to monitor any misalignment between applied input vibration profile and that appears on surface of fixture. Such misalignment between input and feedback (monitor sensor) is shown in Fig. 10. There are many reasons for such type of errors, i.e. after implementing appropriate changes (i.e. improper fixture mounting, incorrect profile, loose sensor mounting, etc.) output profile follows input profile as shown in Fig. 11.
• There should not be any physical contact of reference crystal module with UUT during test.
• Potting is recommended for leaded electronic components to provide rigidity for assembly during test [Reference Howe, Lanfranchi, Cutsinger, Hati and Nelson12–Reference Kumar, Jayasheela, Shivakumar and Manjunath14].
Performance results
This section discusses practically achieved phase noise performance stabilization results in X, Y and Z axis during RV test. RV test is subset of forced vibration in which in spite of single frequency, a spectrum of frequency random in nature applied to system under RV test with pre-defined PSD magnitude. For accessing phase noise performance of PLL frequency synthesizer under harsh vibrational environment, RV test is conducted at magnitude of 7.5 g in three axes inside vibration chamber. During conduction of RV test, applied vibrations of defined PSD get translate on system under testing. To ensure proper conduction of RV test, proper mounting and fastening is must for matching applied PSD profile on system under test. Generated RVs disturb the performance of vibration prone components used in any system, hence need of special compensation mechanisms to reduce its effect is must. Inside view of mounting of reference crystal module which is isolated from rest of the system for reduction in direct translation of vibration effect is shown in Fig. 8. As discussed in earlier section, X-band signal is generated using S-band PLL signal along with frequency multiplier IC. PLL uses 100 MHz reference crystal for synchronization.
PSD spectrum ranging from 20 to 2000 Hz defines amplitude of vibration test as shown in Fig. 11. Realized system has gone for RV test in all three axes of 5 min duration for 7.5 g value. From equations (1) and (2), it is calculated theoretically that ~38–42 dB phase noise degradation factor implies on translation of 100 MHz signal into X-band 10.6 GHz. Phase noise of reference crystal and X-band signal in ambient condition is shown in Figs 12(a) and 12(b), respectively, at three offset frequencies viz. 100 Hz, 1 kHz, and 10 kHz. One hundred megahertz reference signal has phase noise of −109, −131, and −138 dBc/Hz while in X-band as −70, −96, and −95 dBc/Hz at three offset, respectively. High g-value RV affects the phase purity of a piezoelectric material reference crystal. Any phase fluctuation occurrence in reference signal gets directly translated into X-band signal. Phase noise performance of reference signal and X-band signal during 7.5 g RV test without any vibration isolation implemented is shown in Figs 13(a) and 13(b). Significant degradation in phase noise of around ~ 50, ~45, and ~15 dB is observed at offsets of 100 Hz, 1 kHz, and 10 kHz, respectively, in Fig. 13.
Hence to improve the phase noise performance, the implementation of structural analysis, spatial analysis, and stabilization methods (i.e. mechanical and electrical) as per present disclosure are implemented. Significant impact in phase noise stabilization during all axes is achieved. Results of phase noise performance of reference crystal of 100 MHz and X-band signal are shown in Figs 14–16 [Reference Kumar, Jayasheela, Shivakumar and Manjunath14–Reference Kumar and Sarkar16].
i) X-axis RV
ii) Y-axis RV
iii) Z-axis RV
Tables 1 and 2 summarize comparison of phase noise results of reference signal and X-band signal measured before and during (with or without stabilization mechanism) RV.
PV – pre vibration, DVS – during vibration without stabilization, DVWS – during vibration with stabilization.
Conclusion
Structure-borne vibration is routine for many applications, causing degradation in phase noise performance of frequency source systems. This article disclosed methods and techniques for reduction of vibration induced noise on reference crystal-based PLL system. Methods of spatial analysis, innovative design techniques, and precautions are presented for improved phase noise performance. Realized X-band frequency source is experimentally verified at 7.5 g. Implementing all disclosures and findings helps to design a robust design at 10.6 GHz suitable for airborne applications with high vibration affect.
Acknowledgement
The authors acknowledge Mr. Manoj Jain, General Manager, Mr. Manjunath R, Sr. DGM, Mrs. Prashanthi G, DGM, Mr. Ramanarao J V, Manager, Bharat Electronics Limited for their assistance and support to carry out the design and testing. The authors also thank Mr. Rambabu G, Sr. DGM, Mr. Venkatamuni T, DGM, Mrs. Kala N, Manager, Bharat Electronics Limited for their contribution during preparation of manuscript. The authors also thank people who were involved directly or indirectly in this work and had given valuable suggestions.
Conflict of interest
The authors declare that there is no conflict of interests regarding the publication of this article.
Vipin Kumar received B.Tech and M.Tech degree in Electronics and Communication Engineering, RF and Microwave Engineering from GGSIPU, New Delhi, India in 2012 and 2015, respectively. Since 2016 he has been working with Product Development and Innovation Center (PDIC) Bharat Electronics Limited, Bangalore, India in domain of Frequency synthesizers and Wideband receiver projects for Missile applications. He has contributed his M.Tech thesis work published as chapter in book title as Rectangular Dielectric Resonator Antennas © Springer India 2016. He has authored or coauthored technical publications in SCI indexed Journals and IEEE conferences. He is recipient of Best Paper Award in IEEE International Conference on Microwave Integrated Circuits, Photonics and Wireless Networks (IMICPW) 2019 held at NIT Trichy. His current research interests include microwave, millimeter wave broadband and narrowband passive and semi-active components design. https://orcid.org/0000-0002-7219-4196.
R. Sivakumar joined Bharat Electronics in 2001 after completing graduation in Electronics & Communication Engineering from National Engineering College, Tamil Nadu, India. In BEL, he was involved in design and development of VHF and UHF radio modules, PLL and DDS based Synthesizers, SAT-com RT, Mobile Jammers, and up/down converters in various frequency bands. He worked as Senior RF Engineer in Sony Ericsson Mobile communication in the year 2008 and Technical Lead in Honeywell Technologies during year 2010–11. Presently, he is working in Product Development and Innovation Centre, BEL for the design and development of Exciters, Wide band Receivers, modules & sub systems for Radar, EW systems, and Super components.
Jayasheela C S joined Central D&E Bharat Electronics Limited in 2010 after completing graduation in Electronics & Communication Engineering from Government College of Engineering, Hassan, Karnataka. In Central D&E Bharat Electronics Limited she was involved in design and development of high frequency synthesizers and narrowband receiver modules. Her main research interest is in RF passive circuit design. Currently, she is working in Product Development and Innovation Centre (PDIC) Bharat Electronics Limited for the design and development of high precision PLL-based RF synthesizers for strategic electronic application.
Mahadev Sarkar received the B.Tech degree from the Murshidabad Engineering College, University of Kalyani, Kolkata, India. From 2005 to 2008, he was an RF Design Engineer with RF Design Group, Astra Microwave Technologies, Hyderabad. From 2008 to 2011, he was a Design Engineer with the Filters and TMA Design Group, Powerwave Technologies India Pvt. Ltd., Hyderabad. In February 2011, he joined the Product Development and Innovation Centre, Bharat Electronics Limited, Bangalore, India where he is currently involved in broad and narrow band receiver design projects. His current research interests include microwave passive and semi-active components design.
Shailendra Singh received his M. Tech degree in Microwave Electronics from University of Delhi South Campus, New Delhi, India, in the year 2013 and B.Tech degree from Galgotia College of Engineering and Technology, Gr. Noida, India. He is currently working as a Deputy Engineer in Bharat Electronics Limited Bangalore, India. His research interest includes antenna design, digital board testing, and real-time system integration and testing. He has worked in Institute for Plasma research and CEERI-Pilani, India. He has published research papers in international and national journals and conference proceedings.