Introduction
In a transmitter system, the radio frequency (RF) power amplifier (PA) generally consumes most of the DC power. The high peak-to-average power ratios (PAPR) of modern digital communication and broadcast standards tend to reduce average PA power efficiency, as the PA spends most of its operating time at the average P OUT while still needing an operating range that covers the peaks. It therefore becomes necessary to develop PA architectures which can achieve a high efficiency at the average P OUT – a region often referred to as “back-off”. Several techniques have appeared over the last 80 years to meet this requirement including Envelope Tracking/Modulation [Reference Watkins and Mimis1], Doherty [Reference Cidronali, Giovannelli, Maddio, Del Chiaro, Schuberth, Magesacher and Singerl2], Outphasing [Reference Bogusz, Lees, Quaglia, Watkins and Cripps3], and Dynamic Load Modulation (DLM) [Reference Mimis and Watkins4]. These can all be classed as analog techniques, and although capable of good performance, are limited in their dynamic range, and hence ability to efficiently amplify high PAPR signals.
The limited dynamic range has led some researchers to investigate alternative architectures inspired by digital-to-analog converters (DAC). The majority of this though has focused on 1-bit architectures using sigma-delta-modulation [Reference Wentzel, Hossain, Stoppel, Weimann, Krozer and Heinrich5]. Due to the high switching speed needed by the class D output stage, these must be integrated, limiting their P OUT, which rarely exceeding 1 W [Reference Fuhrmann, Moreira, Oßmann, Springer, Weigel and Pretl6]. An alternative to 1-bit architecture exists where multiple amplifiers operate in parallel to recreate the signal envelope. These also tend to be integrated, but this paper will discuss an architecture that can be implemented with discrete devices opening up possibilities of digital power amplifiers (DPAs) operating at transmit powers in excess of 1 W.
This paper is organized as follows: section “Parallel digital power amplifier” discusses the basic parallel DPA architecture and its operation including the target output powers for each state. The critical output transmission line (TL) network is discussed in its own subsection. Simulated results are presented in section “Simulated digital power amplifier results”, including electromagnetic (EM) simulated results of the output network. The practical implementation is discussed in section “Practical implementation”. Practical results are presented in section “Results” and conclusion given in section “Conclusion”.
Parallel digital power amplifier
The basic structure of a DPA consisting of multiple amplifiers connected together with a TL network is composed as shown in Fig. 1. A constant amplitude phase-modulated RF signal is applied to all amplifiers simultaneously. A digital interface D 1−3 enables and disables individual amplifiers for conveying envelope amplitude information to the output. The TL network allows the amplifiers to interact with one another as they are alternatively enabled and disabled. It can be of any arbitrary topology tailored to best suit the application; a vast number of possible topologies exist.
Fig. 1. Three-bit digital power amplifier schematic.
For efficient operation, the amplifiers should operate at or near their saturation point where their individual output voltage swing is at its maximum for a given supply voltage (V DC1−3) and be maintained during all of their particular on-states. Figure 1 consists of three amplifiers with seven on-states and one off-state, resulting in a total of eight. The number of amplifiers can be increased, resulting in a greater number of output states. An amplifier is enabled by applying a voltage just above its threshold voltage (v th) to its gate. This allows it to supply current to the TL network in-phase with that produced by other enabled amplifiers. These currents add in the network and produce an RF voltage output across an RF load. An amplifier is disabled by applying a strongly negative voltage to its gate. A disabled amplifier appears to the TL network as a purely passive network composed only of its stray parasitic components. It is assumed that when disabled, the drain-source capacitance (C DS) dominates, and hence the devices can be approximated as their C DS only.
When an amplifier switches from supplying current to the TL network, to appearing as only CDS, in this way, it will cause a change in the impedance presented to the output port of the other operating amplifiers, an effect which is known as load-modulation [Reference Bousnina7]. Load-modulation is the process that both Doherty [Reference Cidronali, Giovannelli, Maddio, Del Chiaro, Schuberth, Magesacher and Singerl2] and Outphasing [Reference Bogusz, Lees, Quaglia, Watkins and Cripps3] PAs achieve high efficiency at back-off. By changing this impedance, the output current of an individual amplifier and therefore its own P OUT will change. This mechanism enables the complete DPA to achieve its eight unique P OUT states with only three amplifiers. Two possible states for the DPA are shown in Fig. 2. One advantage of this architecture is that the digital inputs operate at baseband rate, as opposed to some DPAs where they operate at the RF carrier frequency [Reference Li, Yin, Zhu, Xiong, Liu, Yan, Min and Xu8]. Simulations in the National Instruments' Microwave Office (MWO) revealed that the C DS of the GaAs devices remained fairly consistent between being enabled with a positive bias and disabled with a large negative bias.
Fig. 2. Three-bit digital power amplifier (a) state 100 and (b) state 101.
To demonstrate the principle, a low-power prototype based around three GaAs FET devices manufactured by Avago/Broadcom was designed. The devices are: ATF50189 for amplifiers 1 and 2, and ATF54143 for amplifier 3. Although low power, these devices demonstrate the ability of this DPA architecture to use discrete devices and therefore the potential to extend it to higher peak P OUTs with the right devices. This moves DPAs away from the worlds of mobile phones and WiFi to base stations and digital TV broadcast transmitters [Reference Dietrich, Wei and Negra9]. Since this work is inspired by DACs, a linear voltage step size is specified. A peak P OUT of 1 W is specified which is approximately 7 Vrms and fits well with all seven on-states. The intended P OUT and V OUT of every state is shown below in Table 1.
Table 1. Target P OUT and V OUT for each state
It will be observed from Table 1 that each amplifier is load-pulled over a large P OUT range. In state 7, all devices should operate near their saturated power and be capable of being load-pulled over a 7 dB P OUT range. This is based on the expectation that amplifier 1 supplies 27 dBm, amplifier 2 26 dBm, and amplifier 3 20 dBm. Amplifier 1 has the easiest job since it needs to only operate over 1.9 dB, compared to the 7 dB of the other two. To prove this hypothesis, the GaAs devices were load-pull simulated in MWO at 500 MHz. The simulated results are shown in Fig. 3 which highlights the expected efficiency for each state.
Fig. 3. Optimum load-pull trajectories, efficiency contours are solid thin lines, P OUT contours dashed and the load-pull trajectories in thick black lines: (a) amplifier 1 and amplifier 2 (ATF50189) and (b) amplifier 3 (ATF54143).
Ideally, each device should trace a load-pull trajectory that bisects all of their required P OUT states, while remaining within a high-efficiency region. The load-pull simulations suggest this is possible, with amplifier 1 staying above 65%, amplifier 2 above 55%, and amplifier 3 above 50%. This assumes that the TL network in combination with the enabling and disabling of the transistors provides enough load-pulling to present the ideal impedances to all amplifiers at all states. Producing a TL network capable of this is challenging, as it is not immediately obvious what topology should be adopted.
Output transmission line network
As a starting point, a TL network inspired by the Rat-Race coupler [Reference Xu, Wang and Lu10] was used. The development of the TL output network from the classic Rat-Race coupler is shown in Fig. 4. This is probably not the optimum network, but was well known to the author from previous work. The ideal load-pull trajectories shown in Fig. 3 track the imaginary impedance plane. How close the DPA tracks these trajectories depends on the topology of the output network and the C DS presented by the amplifiers in their off-state.
Fig. 4. TL output network development: (a) Rat-Race coupler, (b) Rat-Race coupler with difference port removed, (c) TL7 and TL8 combined into TL16 and TL11 and TL12 combined into TL15, (d) 3-input Rat-Race coupler without difference port.
A traditional Rat-Race coupler is shown in Fig. 4(a), where TL1−6 are a quarter wavelength in length and if the coupling ratio is equal to impedances of 70.7 Ω in a 50 Ω system. The difference port is removed in Fig. 4(b), to reduce the power lost at that port when the signals applied to input 1 and input 2 are not equal. A terminated difference port in Fig. 4(a) isolates input 1 and input 2. This is usually a desired feature of a power coupler. In this work though, we specifically want input 1 and input 2 to be non-isolated so that one can influence the other to provide load-pull. In Fig. 4(c), TL7 and TL8 of Fig. 4(b) are combined to form TL16 as are TL11 and TL12 into TL15. The coupler of Fig. 4(c) is extended to the three-input network shown in Fig. 4(d) with the addition of TL19 and TL20. This configuration maintains the sum port with only one TL between it and the additional input (input 3) and also one additional TL to the node between TL21 and TL22 which is equivalent to the node between TL15 and TL16 of Fig. 4(c). This arrangement maintains two paths between each amplifier to encourage load-pull between amplifiers 1–3 shown in Fig. 2. The network developed in Fig. 4 is just one possible topology for a discrete DPA like that described in this work. An almost infinite number of alternatives are available which may provide better performance and will be the subject of future work in this area.
Simulated digital power amplifier results
In the initial stages of the DPA, all TL lengths in the output network were set to a quarter wavelength. The genetic algorithm (GA) optimizer available in MWO was set to tune the lengths and widths of all TLs. GAs have previously been used successfully to optimize the output matching networks of multiband PAs [Reference Arabi, Enrico de Falco, Birchall, Morris and Beach11] and dimensions of planar antennas [Reference Gulati, Siddhartha, Vedi and Susila12]. The optimizer was also able to independently tune the supply voltages (V DS) to the three amplifiers and a fixed delay between them. After tuning during optimization, a consistent delay between the paths was kept for all states. The P OUT goals for the optimizer were set out as in Table 1 with efficiency goals set to >50%. The simplified layout in Fig. 4(d) was modified to include additional TLs between the drain terminal of each amplifier and output network to supply DC current, and bends and joints so that all loops could be maintained resulting in the layout shown in Fig. 5. It will be noted that the port connecting to amplifier 1 is in the middle of the board. This is a drawback of this architecture as it requires RF signal lines to cross over one another. After optimization, the results are presented in Fig. 6.
Fig. 5. Full layout for output network.
Fig. 6. Simulated results of load-pull DPA.
The results in Fig. 6 show that seven unique on-states can be achieved at ≥50% efficiency. V OUT does not follow the linear relationship defined in Table 1, but does show a general progression with a positive gradient. This suggests that the output network proposed in this work provides a partial solution to the problem of trying to present the optimum impedances to the devices at all seven on-states. However, it does suggest that the concept is valid and that other networks may exist which can provide a more complete solution. Peak P OUT is 1.2 W (30.6 dBm). The simulated phase response is shown in Fig. 7, where the phase response of the DPA varies by over 90° across the various states. This can either be compensated by applying the appropriate phase offset when mapping the signal onto the constellation diagram points or with digital pre-distortion (DPD). The variation in phase is likely due to the interaction between the currents generated by amplifiers 1–3 as they load-pull one another.
Fig. 7. Simulated phase response of DPA.
To further evaluate the DPA, its performance was simulated over the frequency band 450–550 MHz, a ±10% range of frequencies. The phase delay of the TLs will vary by the same amount as the frequency is varied, but no changes were made to the DPA from when it was optimized at 500 MHz. Under these conditions, the DPA was able to achieve a good level of performance as shown in Fig. 8. Both the average efficiency over all on-states and the minimum and maximum V OUT for the on-states are recorded. Performance degrades at 450 MHz, where a minimum V OUT of 0.3 V was recorded, not for state 1, but state 4 with a resulting efficiency was only 0.2%. In state 4, only the amplifier 1 is in use. This dramatic drop in performance was not due to the current from amplifier cancelling with another.
Fig. 8. Simulated frequency response, the hatched area is the minimum and maximum V OUT and the black line the efficiency.
EM simulation of output network
During the design phase, it was found that some of the TLs had a larger impact on system performance than others. This led to the need for an EM simulation of the output network to ensure that the correct impedances were presented to the ports. The network shown in Fig. 6 was exported to MWO EMSight simulator as shown in Fig. 9.
Fig. 9. EM model of output network of the DPA; port 1 connects to amplifier 1, port 2 to amplifier 2, port 3 to amplifier 3, and port 4 to the RF output.
The port S-parameter results from the EM simulation after tuning are shown in Fig. 10 where they are compared with the circuit-level simulation of Fig. 5. Simulations are only performed at three frequencies: fundamental (500 MHz), second harmonic (1 GHz), and third harmonic (1.5 GHz). The arrows indicate increasing simulation frequency from 500 MHz to 1.5 GHz. There is a good correlation between the circuit level and EM simulation.
Fig. 10. Circuit (solid) and EM (dashed) simulations of the LT output network port impedances in a 50 Ω domain looking into ports for: (a) amplifier 1, (b) amplifier 2, (c) amplifier 3, and (d) RF output; arrows indicate increasing order of signal component: fundamental, second, and third harmonic zones.
Practical implementation
To further verify the operation, the prototype DPA was fabricated on an FR4 printed circuit board (PCB) substrate including the gate driver circuitry. A photograph of the fabricated DPA is shown below in Fig. 11. Due to the two loops of TL, amplifier 1 (port 1 in Fig. 4) was located in the middle of the PCB surrounded by one of the loops. Its RF input was mounted on the underside of the PCB; the cable connecting to it can be seen in Fig. 6 on the left side. The inputs to amplifiers 1–3 were attached to a three-way Wilkinson Power Splitter by a coaxial cable so that the delay between them can be adjusted with SMA adapters. The digital input is in the top left corner of the board. This was connected with jumpers to a set of dual-in-line package switches which could manually enable or disable amplifiers 1–3 for selecting the different states.
Fig. 11. Photograph of practical DPA.
As stated in section “Parallel digital power amplifier”, the devices are switched between their v th and a strongly negative voltage to disable them. The gate driver circuitry translates standard 0 to +3.3 V logic levels to enable and disable voltage levels for the GaAs FETs. To achieve this, a Si8610BB digital isolator and MCP1402 MOSFET gate driver are used as shown in Fig. 12. The MCP1402 has a peak-to-peak output swing of 5 V. For the ATF-54143 driver, the output swings between 0.3 V, v th of the ATF-54143, and −4.7 V to disable it. For the ATF-50189 v th is 0.4 V, so the driver output swings between 0.4 and −4.6 V.
Fig. 12. Gate driver schematic for the ATF-54143.
Results
A Keysight N5172B EXG signal generator and Keysight N9010A EXA vector signal analyzer were used as a signal source and P OUT monitor, respectively, for the measurements. A Minicircuits ZHL-1-2 W+ amplifier was also included to drive an equal three-way Wilkinson Splitter on the input. The measured results for V OUT and the efficiency for each state are shown in Fig. 13. Seven unique on-states were achievable at ≥40% efficiency with a peak P OUT of 28.9 dBm (780 mW) corresponding to a V OUT of 6.2 Vrms. Although V OUT does not have the desired linear step size, it does have a positive trajectory. Input signal drive to the Wilkinson Splitter was 13 dBm under all states. The Splitter and cable loss when measured was approximately 5 dB, resulting in 8 dBm at amplifiers 1–3 input.
Fig. 13. Measured results.
The measured phase response is shown in Fig. 14, where it can be seen to be relatively flat across states 2–7. This is different from the response shown in Fig. 7. The variation in the response is due to the summation and cancellation between the three amplifiers as they enter compression at different input powers, the amplifier whose output current dominates will dominate the phase response. The phase response can be compensated for either by the constellation diagram mapping or DPD as discussed in section “Simulated digital power amplifier results”.
Fig. 14. Measured phase response.
The minimum V OUT at state 1 was 3.0 Vrms, representing a dynamic range of 6.4 dB. This state achieved the highest efficiency of 51%. The discrepancies between simulation and measurement were like due to limitations of the GaAs FET models and the port impedance discrepancies of the output network noted in Fig. 8. The performance achieved is compared to similar published architectures as shown in Table 2 where it performs favorably. References [Reference Fuhrmann, Moreira, Oßmann, Springer, Weigel and Pretl6], [Reference Bhat and Krishnaswamy13], [Reference Watanabe and LaRocca14], and [Reference Quach, Watson, Dupaix, Barton, LaRue, Gouty and Khalil15] achieved a higher peak P OUT, but backed-off efficiency (η) was significantly lower. Back-off efficiency is more of a useful metric when modulated signals are used. This was even for the case of the two GaN MMIC implementations [Reference Watanabe and LaRocca14, Reference Quach, Watson, Dupaix, Barton, LaRue, Gouty and Khalil15], although these were operating at significantly higher frequencies. Comparing this work to the GaAs implementation of [Reference Watkins16], there does not appear to be a significant impact by operating frequency on efficiency.
Table 2. Comparison of parallel DPAs ranked by peak P OUT
a Estimated from available information.
Conclusion
This paper describes a new parallel DPA architecture using discrete devices whose outputs are connected together with TL network inspired by a Rat-Race combiner. A 3-bit prototype was developed with a GA used to optimize the TL network. The simulation model achieved a peak P OUT of 29.7 dBm with all seven on-states at ≥50% efficiency overall states. The practical demonstrator had a peak P OUT of peak power of 28.9 dBm with on-state efficiencies ≥40%. This work represents the first discrete device DPA know to the author which makes it scalable to higher P OUT, and therefore realizing applications like base-stations and digital TV broadcast transmitters with DPAs becomes a reality.
Acknowledgements
The author would like to thank all at Toshiba Research Europe Limited for their support and advice with this work.
G. T. Watkins is a member of both the Institute of Engineering Technology (IET) and the European Microwave Association. He received the MEng degree in Electrical and Electronic Engineering in 2000 from the University of Bristol and a Ph.D. from the same institution in 2003. In 2008, he joined Toshiba Europe Limited where he is currently the lead for the Analogue and Digital Systems Programme. He is also the vice chair for the IET RF and Microwave Technical Network and a Senior Visiting Research Fellow at the University of Bristol. He is the recipient of a Toshiba Innovation Award for his work on high-efficiency FM broadcast transmitters, the 2015 Best Paper Award from the International Journal of Microwave, and Wireless Technology and the 2019 IET Premium Award. His research interests include linear power amplifiers, active gate drivers, device characterization, 3D printing for RF, and Full Duplex communication systems.
