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Laser–Assisted Mos/Sos Transistor Fabrication*
Published online by Cambridge University Press: 15 February 2011
Abstract
CW laser annealing techniques were incorporated into standard MOS/SOS transistor fabrication procedures and found to be advantageous as compared to conventional furnace methods for electrical activation of ion–implanted source/drain dopants for both N- and P–MOS transistors. Static electrical characteristics of 2.4 μm channel–length transistors are similar for both types of annealing, whereas the speed of devices with cw laser annealed source–drain regions is increased 10 to 40%, depending on the operating voltage.
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- Research Article
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- Copyright © Materials Research Society 1982
Footnotes
Supported in part by U.S. Army ERADCOM, Contract No. DAAK20–80–C–0269.
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