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A Complementary Wafer Cleaning and Growth Process for Low Temperature, Defect Free, Selective Silicon Epitaxy

Published online by Cambridge University Press:  25 February 2011

Jon T. Fitch  and
Dean J. Denning
Jon T. Fitch
Affiliation:
Motorola Inc., Advanced Products Research and Development Laboratory, MD-K10, 3501 Ed Bluestein Blvd., Austin, TX 78721
Dean J. Denning
Affiliation:
Motorola Inc., Advanced Products Research and Development Laboratory, MD-K10, 3501 Ed Bluestein Blvd., Austin, TX 78721
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Abstract

Low temperature (<850°C) defect free selective silicon epitaxy has been achieved with a conventional barrel type reactor (base pressure -10−4 Torr) using complementary cleaning and growth processes: a wet multi-step oxidizing clean, and a novel non-steady state CVD growth process. With this combination of cleaning and growth processes, it is shown that the need for a high temperature (950-1000°C) insitu native oxide removal step, which may be incompatible with advanced VLSI process integration, is eliminated.

Type
Research Article
Information
MRS Online Proceedings Library (OPL) , Volume 259: Symposium B – Chemical Surface Preparation, Passivation and Cleaning for Semiconductor Growth and Processing , 1992 , 487
Copyright
Copyright © Materials Research Society 1992

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References

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