Design and analysis of the proposed power divider

Figure 1(b) shows the presented Gysel HMSIW power divider. It consists of a HMSIW ring, three HMSIW-microstrip gradual taper transitions, and two microstrip stubs to assemble two isolation resistors. It is obvious that the heat of the transmission lines can be radiated to the atmosphere rapidly and effectively because of the large radiating area, and removed to the ground plane (heat sinking) through the via holes. Then, compared with the traditional microstrip Gysel power dividers, the relative low temperature of the presented HMSIW Gysel power dividers can be kept under the condition of high input power (such as more than 100 W).

Good impedance matching can be implemented by using the HMSIW–microstrip taper transitions. The length between the input port and the output port are chosen to λg/4 (λg is the guided wavelength of HMSIW at the center frequency), while the HMSIW ring's length between two isolation resistors is λg/2. Moreover, the length of the two microstrip stubs L1 is also chosen to be λg/4 to achieve the impedance matching between the HMSIW ring and the isolation resistors. The even- and odd-mode analysis method can be applied to analyze and design the presented Gysel HMSIW power divider due to the circuit symmetry. If two signals of same amplitude and in phase (even mode) are applied at two output port, by symmetry a voltage maximum occurs at every point on the line of symmetry. That is, at these points Z = ∞. This is the equivalent of an open circuit as illustrated in Fig. 2(a) and the O, C represent open circuit. Similarly, if two signals of same amplitude and out of phase (odd mode) are applied at two output port, a voltage minimum occurs at every point on the line symmetry. That is, at these point Z = 0. This is the equivalent of a short circuit as illustrated in Fig. 2(b) and the short circuit is grounded.

Fig. 2. Even- and odd-mode equivalent circuit of the presented power divider: (a) even mode, (b) odd mode.

The even and odd mode analysis can simplify the circuit. With even mode excitation and odd mode excitation, the simplified circuit can be analyzed, respectively. Figure 2(a) shows the even-mode circuit model for a bisection of this power divider. Firstly, it gives the impedance/admittance analysis of the parts of the even mode circuit. The input impedance is Z ₀, as for a bisection of input post, the input impedance is 2Z ₀. It is the same as micro taper which is 2Z _T(x) in the even mode circuit. The characteristic impedance Z _T(x) of the microstrip taper can be given by

(1)$${\rm Z}_T(x) = \displaystyle{{120\pi /\sqrt {\varepsilon _e}} \over {w(x)/d + 1.393 + 0.667\ln [w(x)/d + 1.444]}},$$

where w(x) = [x(w ₁ − w ₀) + w ₀L ₀]/L ₀ and x is the position along the taper. So the reflection coefficient and the input admittance of the gradual taper at x = L ₀ is given by

(2)$$\Gamma _{{\rm in}1} = \displaystyle{1 \over 2}\int_0^{{\rm L}_0} {e^{ - j2\beta {\rm x}}\displaystyle{{d[\ln 2Z_T({\rm x})]} \over {d{\rm x}}}} d{\rm x} + \Gamma _L,$$

(3)$$Y_{e3} = \displaystyle{{1 - \Gamma _{{\rm in}1}} \over {(1 + \Gamma _{{\rm in1}})2Z_T(L_0)}}.$$

The total input admittance Y _e can be expressed as

(4)$$Y_e = Y_{e1} + Y_{e2},$$

where

(5)$$Y_{e{\rm 1}} = Y_1\left( {Y_{e3} + jY_1\tan \theta _1} \right)/\left( {Y_1 + jY_{e3}\tan \theta _1} \right),$$

(6)$$Y_{e{\rm 2}} = Y_1\displaystyle{{Y_r + jY_1(\tan \theta _2 + \tan \theta _4)} \over {Y_1 + j(Y_r + jY_1\tan \theta _4)\tan \theta _2}},$$

where Y ₁ is the characteristic admittance of HMSIW and

(7)$$Y_r = \displaystyle{{Z_2 + jR_L\tan \theta _3} \over {Z_2(R_L + jZ_2\tan \theta _3)}}.$$

Moreover, the reflection coefficient Γ_e can be given by

(8)$$\Gamma _e = \left( {1 - Y_eZ_T(w_1)} \right)/\left( {1 + Y_eZ_T(w_1)} \right).$$

The input reflection coefficient Γ_ine at port 2 can be given by

(9)$$\Gamma _{{\rm in}e} = \displaystyle{1 \over 2}\int_0^{L_0} {e^{ - j2\beta {\rm x}}\displaystyle{{d[\ln Z_T({\rm x})]} \over {d{\rm x}}}} d{\rm x} + \Gamma _e,$$

with the help of the formulas above, the desired input reflection coefficient of the presented power divider can be analyzed and synthesized. For example, according to (9) and the circuit sizes can be determined under the desired circuit design parameters (such as central frequency, bandwidth, return loss, etc.).

Under the odd-mode excitation, a bisection of the power divider is shown in Fig. 2(b). The input admittance Y_o can also be expressed by

(10)$$Y_o = Y_1\displaystyle{{Y_r + jY_1(\tan \theta _2 - \cot \theta _4)} \over {Y_1 + j(Y_r - jY_1\cot \theta _4)\tan \theta _2}} - Y_1\cot \theta _1.$$

When θ ₁ = θ ₂ = θ ₄ = π/2,Y _e = Y _o = 1/Z _T(w ₁), good impedance matching can be achieved, and (4) and (10) can be reduced as

(11)$$Z_1 = \sqrt 2 Z_T(w1),$$

(12)$$R_L = Z_2^2 /Z,$$

where Z ₁ is the characteristic impedance of HMSIW. Equations (11) and (12) provide a simple guideline in the selection of Z₁ and R_L.

The even and odd mode analysis gives rough design parameters of the power divider. Furthermore, the power divider needed to optimize by commercial simulation software accurately.

Experimental results

Based on the design procedure discussed above, a Gysel HMSIW power divider has been designed. The Taconic RF-35 substrate with a relative dielectric constant of 3.5, the thickness of 0.508 mm, loss tangent of 0.0018 is used. The commercial software HFSS is used for optimizing the proposed power divider. The photograph of the fabricated power divider is shown in Fig. 3. The final sizes of this circuit are (unit: mm): L ₀ = 8.5, L ₁ = 6, L ₂ = 11, L ₃ = 19.5, L ₄ = 5.85, s = 0.9, d = 0.5, W ₀ = 1.11, W ₁ = 4.5, W ₂ = 1.6, W ₃ = 12.4, W ₄ = 17.2, R _L = 70 Ω.

Fig. 3. Photograph of the fabricated power divider.

Figure 4 shows the measured and simulated input return loss and insertion loss of the fabricated HMSIW power divider. The simulated input return loss is greater than 15 dB from 4.65 to 5.45 GHz, while the measured one is greater than 15 dB from 4.7 to 5.7 GHz and greater than 25 dB in the frequency range of 4.9–5.56 GHz. The simulated 1-dB insertion loss bandwidth (the 3 dB power division loss is not included) is about 900 MHz (4.8–5.7 GHz), while the measured one is about 850 MHz (4.8–5.65 GHz). The measured minimum insertion loss is about 0.7 dB. Compared with the simulation results, the increased insertion loss is most likely attributed to the fabrication error and the loss of the SMA connectors, which are not included in the simulation model.

Fig. 4. Simulated and measured input return loss and insertion loss.

Figure 5(a) shows the simulated and measured output return losses. It can be seen that the simulated output return loss is greater than 14 dB from 4.65 to 5.5 GHz, while the measured one is greater than 15 dB from 4.8 to 5.65 GHz. Moreover, the measured isolation is greater than 15 dB in the frequency range of 4.95–5.75 GHz, as shown in Fig. 5(b). It can be seen that a measured maximum amplitude imbalance of ± 0.2 dB and a phase imbalance of ± 2° are observed from 4.6 to 5.8 GHz. Table 1. shows the comparison with other HMSIW power dividers in recent years. It demonstrates that this work has realized the better performance of isolation, input/output return loss, and compact size.

Fig. 5. Simulated and measured results: (a) output return loss and Photograph of the fabricated power divider, (b) isolation, magnitude, and phase imbalance.

Table 1. Comparison with other HMSIW power dividers