Introduction
Doherty Power Amplifier (DPA) has been now widely accepted as an off-the-shelf radio-frequency power amplifier (RFPA) solution to improve the energy efficiency of 3 G–4 G base stations and is on track to lead the competition in future 5 G transmitters [Reference Asbeck1]. Although it suffers from inherent limitations, mainly due to the frequency selective output combining circuit, several works have highlighted the DPA capabilities to accommodate a typical 20% fractional bandwidth [Reference Piazzon, Giofrè, Colantonio and Giannini2–Reference Coffey, MomenRoodaki, Zai and Popovic4], while advanced DPA structures have been demonstrated to operate over fractional bandwidth up to 80% [Reference Moreno Rubio, Camarchia, Pirola and Quaglia5], at a cost of a reduced load modulation effect, introducing the so-called Doherty-lite topology.
When implemented with a conventional analog input radio frequency (RF) splitter, the DPA AB-C topology suffers from several degradations, among which:
(i) Gain roll-off between low and high power regions, due to the deep class-C transistor operation of the auxiliary amplifier
(ii) Output power and efficiency discrepancy due to dispersive AM-PM and AM-AM conversions of transistors that combine their currents out-of-phase in a frequency-selective load.
Taking advantage of the low power, commercially available dedicated circuits (e.g. ASICs, DSP), the digital version of the DPA has been introduced and is now viewed as a potential competitive embodiment for future DPA [Reference Darraji, Ghannouchi and Hammi6–Reference Andersson, Gustafsson, Chani Cahuana, Hellberg and Fager9]. In related implementations, the fixed input RF splitting circuit is advantageously replaced by a fully reconfigurable power-dependent RF distribution between Main and Auxiliary cells of the DPA. Doing so, this enables to optimize the beneficial load–pull interaction between power cells, and maximize linearity/efficiency DPA performances.
At the system designer level, (Massive) MIMO access techniques are widely envisaged as a potential breakthrough to mitigate harsh microwave/millimeter wave propagating conditions and to improve the capacity of future 5 G integrated RF systems. Because of high integration, the flip side is that severe constraints are reported on analog microwave front-end elements, leading to e.g. higher levels of coupling and a higher level of power density to dissipate. Highly integrated millimeter-wave active antenna (e.g. active electronically scanned array (AESA), for radar or communication applications), is of typical interest to exemplify this point. By suppressing the lossy and bulky isolators between RFPAs and radiating ports, RFPAs are subjected to significant voltage standing wave ratio (VSWR) values, degrading the overall linearity and efficiency performances [Reference Jordão, Belo, Caldeirinha, Oliveira and Carvalho10–Reference Hu, Kousai and Wang12].
This paper presents some theoretical backgrounds giving insight into the conventional DPA behavior when used in a realistic mismatched load environment. It is described how DPA power performances can be partially recovered by monitoring the magnitude and phase of the RF signal at the auxiliary path input. The paper is organized as follows. The section Theoretical assumptions presents the theoretical assumptions made on the active devices that will be used in the DPA structure. In the section DPA theoretical performances analysis under matched-load configuration, DPA performances are derived in a conventional 50-Ω system impedance reference. The section Dual-input DPA theoretical behavior under mismatched load highlights the degradations that occur when the output load impedance is pulled-away from its nominal value and shows how the DPA architecture is theoretically able to mitigate these degradations. The section Dual-input DPA prototype simulation presents a C-band, 20W GaN DPA prototype including dual-input capabilities, and simulated harmonic balance (HB) performances are discussed. Finally, measurement results of the fabricated prototype are presented in the section Dual-input DPA prototype measurement and validate the proposed study.
Theoretical assumptions
Transistor model used for the proposed analytical study is considered as a piecewise linear transconductive current source. The knee voltage (V k) is neglected and the biasing voltage (V DD) is chosen so that the avalanche phenomenon is avoided. No reactive part is considered (e.g. package effect and extrinsic device parasitics). This very simple model gives sufficient insight into the DPA behavior, provided that large-signal voltage clipping is avoided. The I-V characteristic is represented in Fig. 1. The maximum current of the device I max is considered to be 1 Amp. The maximum sustainable drain-source voltage V max is 80 V. These values are typical for a 6W, 1 mm-periphery GaN HEMT power device.
Fig. 1. Simplified I-V characteristic of transistor.
Considering class-B operation, transistor is sinking fundamental current I fund and DC current I DC that is given in (1), wherein the a coefficient is the normalized RF drive amplitude. We assume that harmonics of current are properly shorted.
Device's maximum active power is obtained at full current and voltage RF swings and is given in (2), where V DD is the drain-to-source bias voltage of the device.
The associated optimum loading resistor R opt is defined by:
DPA theoretical performances analysis under matched-load configuration
The DPA architecture is presented in Fig. 2. Based on theoretical assumptions, previous Main and Auxiliary devices are directly implemented through current sources injecting fundamental currents I main and I aux. These currents are combined through a lossless output RF circuit, namely a λ/4 and a λ/2 composite transmission lines, in which the reactive parasitics of the transistors are absorbed, and a common (real) load R c, defined as:
Fig. 2. Doherty power amplifier (DPA) topology.
This constitutes an inverted Doherty amplifier topology. The n factor is introduced to account for generalization in the DPA structure, in which the Auxiliary device could be n times larger than the Main one. This enables larger modulation ratios and thus larger OBO peak-efficiency operation for the DPA. Throughout this paper, I main is considered as the phase reference, and is real. The phase offset Φ is thus defined as:
Using ABCD matrixes of λ/4 and λ/2 transmission lines, one can derive (6) that indicates that the output common node voltage V c (i) is solely a function of the Main fundamental current I main and the characteristic impedance Z 0, and (ii) is phase-inverted and copied at the intrinsic Auxiliary drain.
Thus, the intrinsic impedance presented to the Auxiliary device is not affected by any load mismatch that appears at the common node. From this simple ascertainment, it is of particular interest to evaluate the ability of the DPA structure to accommodate with output load mismatch by controlling the amplitude and phase of I aux.
First, we suppose there is no load mismatch (Z load = 50 Ω). The relationships between fundamental voltages and currents are derived from the ABCD-matrixes of the quarter-wave inverter, the λ/2 transmission line and the common load R c, giving:
The active powers of the Main and Auxiliary devices are given in (8), in which a 1, a 2 represent the normalized amplitude controls and Φ represents the phase control of the two devices, as defined in Fig. 2 :
Provided that the output combiner is lossless, these powers sum up to give the total active power transferred to Z load:
The global DPA efficiency is thus given by:
The efficiency function is plotted in Fig. 3 for different a 2 values and for n = 1 (symmetrical DPA).
Fig. 3. DPA efficiency curves (dot – blue) calculated according to (10) (n = 1) and maximum realizable efficiency of the DPA (circle – red).
To calculate the maximum achievable efficiency of the DPA, constraints must be added to account for the physical limitations of the devices, namely:
Main and Auxiliary voltages are given by :
The Fresnel representation of voltages (normalized to V DD) $\overline {V_{main}}$
and $\overline {V_{aux}}$
is plotted in Fig. 4.
Fig. 4. Fresnel representation of fundamental voltages in DPA architecture (from (11)).
To ensure maximum efficiency operation within the 0 ≤ a 1 ≤ 1 range, the auxiliary device remains off in the 0 ≤ a 1 ≤ a 1th range, with the threshold point defined as:
For a 1th ≤ a 1 ≤ 1, the auxiliary device comes into play to modulate the load impedance of the main transistor, producing a constant and purely real voltage V main equal to V DD. The corresponding value of a 2 to reach maximal efficiency is given by:
which can be written in polar form as:
Current, voltage, and load impedance variations versus a 1 are represented in Fig. 5, with n = 1. This corresponds to the well-known ideal symmetrical DPA operation.
Fig. 5. Fundamental voltage, current and impedance variations versus a 1 in ideal DPA operation.
Dual-input DPA theoretical behavior under mismatched load
Load impedance variations at intrinsic planes
We will extend the previous analysis to the case of mismatched load impedance. Z load is now modified such that Z load = 50 ζ load [Ω]; with ζ load = (r + jx) being the normalized mismatched load impedance. Four typical cases will be studied, namely:
These load impedances are located in a constant 1.5-VSWR locus, as illustrated in Fig. 6, and correspond to a mismatched environment that can occur in AESA applications.
Fig. 6. Studied Z load (constant 1.5-VSWR) in DPA realistic mismatched configuration.
The relationship between voltages and currents is given by
V main and V aux are plotted in Fig. 7, along with associated load impedance variations in Fig. 8, for the four mismatched load conditions, and for the same optimum drives as derived in the 50-Ω nominal case. For the sake of clarity, arg(V aux) is not reported, because it remains in quadrature with a 1, and is not altered by the mismatch effect, as described in the section Theoretical assumptions.
Fig. 7. V main and V aux variations versus a 1 in mismatched load configuration.
Fig. 8. Impedance trajectories at intrinsic planes of Main and Auxiliary devices; the Main impedance is modulated from (1 + n)ζ loadR opt (back-off operation) to (1 + n)ζ loadR opt − nR opt (saturated power condition), Auxiliary impedance is modulated from Open Circuit (O.C) to R opt/n.
When the 50 ohms matched-configuration optimum RF drives are maintained (e.g. because of a fixed splitting configuration), efficiency and linearity performances of the DPA are strongly affected.
When a resistive load-pull occurs (Z load = Z re+), V main can reach higher values than V DD, potentially strongly affecting the linearity of a real-life DPA and even causing reliability issues to the Main device. When Z load = Z re−, V main is always lower than V DD, reducing the net active power delivered to the load, and impacting the overall efficiency of the DPA.
When a reactive load-pull effect occurs (Z load = Z im− or Z im+), V main is no longer in phase with I main, and has magnitude higher than V DD above the threshold point a 1th, both contributing to produce a constant net active main power, and thus do not impact the global efficiency of the DPA. The active powers injected by the Main and Auxiliary devices are given by:
The active powers delivered by both transistors sum up to give the active power transferred to the load, which is independent of the Φ value and is a function of the real part of the mismatched normalized load impedance. The resulting efficiency function is given in (19) and is plotted in Fig. 9.
Fig. 9. Drain efficiency performances of the DPA when load-pull occurs at the output plane; !! annotation means that electrical constraints are not satisfied (e.g. |V main| > V DD).
DPA performances with optimal-efficiency RF drives
The new maximum-efficiency driving conditions are sketched in the Fresnel representation of the voltage vectors V main and V aux. As it can be seen in Fig. 10, they are dependent on the load-pull presented at the output of the DPA structure. Again, to ensure maximum-efficiency operation, the auxiliary transistor is off in the 0 ≤ a 1 ≤ a 1th range, with:
Fig. 10. Fresnel representation of the fundamental voltages V main and V aux for load mismatch conditions.
For a 1 = a 1th, the produced complex main voltage is:
In the $a_{1\_th} \le a_1 \le 1$
range, the auxiliary device comes into play to modulate the complex impedance presented to the main transistor, producing an out-of-phase drain-to-source voltage with a constant V DD magnitude. The corresponding optimal efficiency drive is thus given by:
which can be written in polar form as:
It can be inferred that when load-pull occurs such that |ζ load| > 1, the optimum drive implies |a 2| > 1 at full RF power in order to maintain the |V main| = V DD condition. For this purpose, a larger auxiliary device should be used, even in a symmetrical DPA topology. The DPA optimum RF drives associated with the four impedance configurations are represented in Fig. 11. As shown in Fig. 12, associated optimal impedance loci move along constant Q trajectories, depending on the load mismatch (with Q = x/r).
Fig. 11. RF drives for optimal efficiency of DPA (n = 1) for the studied mismatched loads.
Fig. 12. Impedance trajectories when optimal RF driving conditions for maximum efficiency are applied (illustrated here for n = 1): Main impedance is modulated from (1 + n)ζ loadR opt (back-off operation) to R opt ζ load/|ζ load|(saturated power condition), Aux. impedance is modulated from Open Circuit (O.C) to R opt/ζ load(1 + n − 1/|ζ load|).
When optimum RF drives a 1, a 2, and Φ are applied, maximum efficiency is recovered, taking into account the physical constraints of sustainable voltages V main and V aux. The optimal efficiency function is represented in Fig. 13 for the four cases of interest. The ratio κ Eff between the efficiency for 50 Ω load (ζ load = 1)) and the efficiency for the mismatched load (ζ load ≠ 1) with optimal RF drives at a 1 = a 1th (at turn-on point) is:
Fig. 13. DPA efficiency performances when optimal RF drives are applied for the studied mismatched load.
The corresponding auxiliary turn-on point shift is:
These quantities are synthesized in Table 1. Non-physical results (e.g. when associated electrical constraints are not satisfied) are annotated with !!. For example, from Table 1 it is not possible to ensure the same maximum DPA efficiency of 78.5% when resistive load-pull occurs, with a shift of the turn-on point. On the contrary, it is not possible to maintain maximum efficiency performances while fulfilling the device's constraints when reactive output load-pull exists.
Table 1. DPA performances with and without optimal drives in mismatched environment. (!!) is put when circuit constraints are not satisfied.
Dual-input DPA prototype simulation
DPA prototype performances under matched-load configuration
A 20 W, C-band, dual-input symmetrical DPA prototype has been built to validate the proposed theoretical study. Commercially available Wolfspeed GaN HEMT packaged components [13] and nonlinear transistor model have been used in HB simulation in Keysight ADS CAD environment. The layout of the final prototype is presented in Fig. 14.
Fig. 14. Layout of the symmetrical dual-input GaN DPA prototype.
An optimum intrinsic load R opt of 34 Ω at 41 dBm output power has been determined. Large-signal simulated performances of the DPA are presented in Fig. 15, at a center frequency of 3.9 GHz. Main and Auxiliary gate to source bias voltages has been adjusted to ensure the correct DPA behavior in nominal 50 Ω loading condition (V GGmain = −3V and V GGaux = −6V).
Fig. 15. DPA prototype simulation results at center frequency of 3.9 GHz in the nominal case (Z load = 50Ω).
We define the power and phase RF imbalances between Auxiliary and Main devices as ΔP and ΔΦ, respectively, as:
In this case, optimum power and phase driving offsets (ΔP = 0dB and ΔΦ = 80°) are in good agreement with expected theoretical values in the section Dual-input DPA theoretical behavior under mismatched load. In the following, current and voltage quantities at the fundamental frequency will be analyzed and all phases will be referenced to I Main, resulting phasors are denoted with the N subscript.
Load modulation effect is clearly observed, as the intrinsic Main device impedance is modulated from 59 Ω to 34 Ω, following a real-to-real impedance locus. Meanwhile, intrinsic Auxiliary device impedance is modulated from open circuit condition to 34 Ω. It can be shown in Fig. 15 (top left) that the Main device is effectively kept saturated in the load-modulation region, giving back-off efficiency improvements as it can be seen in Fig. 15 (bottom left).
DPA prototype performances under output mismatch configuration
The same load mismatch conditions studied in the theoretical section have been applied to the prototype DPA. First, the static CW optimum matched-case splitting conditions (ΔP = 0dB and ΔΦ = 80°) are maintained. Associated modified load impedance variations are reported on Fig. 16, and are in good agreement with theoretical trends shown in the section Dual-input DPA theoretical behavior under mismatched load.
Fig. 16. Distorted intrinsic Main and Auxiliary impedances in mismatched load configuration.
Associated intrinsic voltages and currents are plotted in Fig. 17, to illustrate how mismatch conditions can adversely affect the DPA behavior. As predicted in the theoretical section, it can be clearly confirmed in Figs 16 and 17 that, as the output impedance is shifted from low value to high value along the resistive part (i.e. for Z re− and Z re+ loading conditions, respectively), the net fundamental voltage produced across the main transistor increases.
Fig. 17. Voltages produced across Main and Auxiliary devices. Reference 50 Ω case is plotted for comparison.
This could potentially induce reliability and linearity issues in the DPA structure. In our case, thanks to the inverse class-F operation employed in the proposed design the net value of the fundamental frequency component of the drain voltage can reach higher values than the theoretical limit of 28 V (i.e in the order of 34 V).
When a reactive load-pull effect occurs (i.e. for Z load = Z im− or Z im+), the Main device impedance is shifted along a constant reactance locus, as theoretically predicted in Fig. 8. In this case, V main is no longer in phase with I main. Its phase depends on the RF drive level, while its magnitude is always higher than its nominal V DD − V k value in the load-modulation range, causing linearity and reliability issues in the DPA structure. Drain efficiency profiles are plotted in Fig. 18 for the four tested impedances. It is verified that, in this typical case, DPA efficiency is strongly impacted in the case of a resistive load pull, and is only slightly dependent on a reactive load pull.
Fig. 18. DPA simulated PAE performances for mismatched load impedances.
Optimum input splitting parameters ΔP and ΔΦ have then been applied to mitigate efficiency power performance decrease. ΔP and ΔΦ are derived according to the procedure described in the section Dual-input DPA theoretical behavior under mismatched load, so that:
• Fundamental voltage produced across intrinsic Main device is restricted by the V DD − V k = 30 V, defined as a target value, so as to ensure optimum safe saturated conditions of devices
• Associated impedance Z Main is modulated along a constant Q trajectory. Q is defined according to the output load mismatch, as x/r.
Optimum Main and Auxiliary currents and intrinsic load impedances are plotted in Figs 19 and 20. They are consistent with theoretical profiles, as it is confirmed that:
(i) A resistive load-pull (Figs 19 and 20, top and bottom left), implies an Auxiliary device turn-on point shift and a maximum available current quantity modification, with no modification on the phase
(ii) A reactive load-pull (Figs 19 and 20, top and bottom right) implies only a phase shift.
Fig. 19. Optimum dual-input DPA prototype fundamental current profiles. Reference 50 Ω case is indicated for comparison.
Fig. 20. Impedance trajectories at intrinsic planes of Main and Auxiliary devices when optimal RF driving conditions are applied.
It is worth noting that, to ensure a constant Q value, ΔΦ has to be slightly modified versus the RF level, which is not predicted in the theoretical section. This is mainly to compensate for the difference of nonlinear AM-to-PM conversions of the devices.
Associated voltages produced across the Main and Auxiliary devices are plotted in Fig. 21. It is verified that a constant fundamental magnitude voltage of V DD − V k = 30 V is maintained for the Main transistor within the modulation range. Simulated best constrained-efficiency profiles at 3.9-GHz (center frequency) are reported in Fig. 22. For comparison, the efficiency profiles without optimal RF drives have been reported, along with the matched-configuration initial DPA performances. Simulated DPA efficiency performances when the working frequency is varied are reported in Fig. 23 (across 300-MHz of bandwidth, approximately 8% of fractional bandwidth, representing a typical use case). They are obtained while keeping the same (optimal) RF driving conditions, derived at the center frequency. It shows that, although the overall performances of the DPA are subjected to RF deviations, mainly because of the inherent dispersive nature of the output combiner, a quasi-static approach is sufficient for such moderate RF bandwidth.
Fig. 21. Simulated voltages produced across Main and Auxiliary devices when optimal RF drives are applied.
Fig. 22. Simulated DPA prototype efficiency at the center frequency of 3.9 GHz, with and without optimal RF drives simulated. Reference 50 Ω case is reported for comparison.
Fig. 23. DPA efficiency profiles when the frequency is varied ±150 MHz from the central frequency (8% of fractional bandwidth). Reference 50 Ω cases are reported for comparison.
Figure 24 shows the associated intrinsic Main and Auxiliary device load lines at the center frequency and at saturated power condition (around 43dBm of output power), and highlights related large-signal reliability issues. It is of particular interest to note the RF stress reduction of the Main device in Z re+, Z im+ and Z im− mismatched load condition thanks to the application of the appropriate RF drives (implying a larger Auxiliary device in Z re+ case, as it can be seen on the I-V trajectory, and as predicted in the theoretical section).
Fig. 24. Simulated intrinsic loadlines of the Main (red circles) and Auxiliary (blue crosses) devices in mismatched environment with and without optimal input RF drives.
Dual-input DPA prototype measurement
To fully validate the proposed study, the DPA prototype has been fabricated and tested in a dedicated experimental test bench (Fig. 25). The set-up uses a tailored calibration procedure to ensure phase and amplitude consistency at the DUT input planes. Output load is varied thanks to a calibrated tuner, and DUT available RF powers and DC consumption are monitored. Detailed informations on the calibration procedure and set-up can be found in [Reference Reveyrand, Courty, Portelance, Medrel, Bouysse and Nébus14].
Fig. 25. Fully calibrated dual-input experimental test set-up.
Thanks to the dual-input driving capabilities of the test set-up, optimal input RF splitting conditions are accurately extracted by sweeping the RF amplitude and phase distribution between Main and Auxiliary paths, as explained in the section Dual-input DPA prototype simulation. Measured DPA drain efficiency performances are plotted in Fig. 26. Measurements have been carried out at a frequency of 3.6 GHz for the two most representative Z Re+ and Z Re−.
Fig. 26. Measured DPA prototype efficiency performances under mismatched load condition (upper: Z Re−, lower : Z Re+). Nominal 50-Ω matched performances are reported for comparison.
It is experimentally confirmed that when the output load impedance is pulled-away from its nominal 50-Ω value, DPA efficiency and power performances are strongly affected, in the way defined in the theoretical section.
For the Z Re− case (Fig. 26, up), backed-off efficiency is degraded whatever the ΔP-Δφ imbalance configuration compared with the nominal 50-Ω matched case. As the RF input level is augmented, it becomes possible to mitigate such degradation, even having higher efficiency compared with the 50-Ω optimal drives. The useful modulating range is however reduced compared with the nominal case, as predicted in Table 1.
For the Z Re+ case (Fig. 26, bottom), efficiency at back-off is improved compared with the nominal 50-Ω case. However, due to the early saturation of the main active device peak-power efficiency is always degraded. Useful modulating range is augmented compared with the nominal case, as predicted in Table 1. As explained, in this typical configuration, flexible RF splitting capabilities can be advantageously used to reduce main device RF stress.
Conclusion
This paper presents theoretical aspects of the DPA topology when used in load mismatch environment. Such conditions can occur in typical AESA RF/microwave subsystems, where DPA can be envisaged as a potential PA topology to mitigate power and efficiency performance degradations. Dual RF input DPA is envisaged as a promising embodiment of the DPA, allowing flexible amplitude and phase distribution of the RF signals to the active cells and thus optimizing their interaction through the non-isolated lossless combining circuit. From a simplified approach, it has been demonstrated how DPA can cope with VSWR thanks to its inherent load-pulling effect. Maximal realizable efficiency profiles have been derived for a single-stage symmetrical DPA configuration, but can be easily generalized for asymmetrical (n ≥ 1) topologies. A dual-input DPA prototype has been built and experimental measurements corroborate the proposed theoretical study. Results give useful insights into optimal circuit selection (e.g. device periphery ratios, bias selection) and offer clear perspectives to design optimal DPA driver stages.
Alexis Courty was born in Limoges, France, in 1993. He received the Master degree and Ph.D. degree in Electrical Engineering from the University of Limoges, France, in 2016 and 2019, respectively. He is currently with Ampleon, Toulouse, where his main field of interest is high-efficiency RF/microwave PAs.
Pierre Medrel received the Ph.D. degree in electronics from the University of Limoges, France, in 2014. From 2014 to 2015, he was a post-doctoral Scientist at the IMS laboratory, Bordeaux, France. He is now an associate professor with the XLIM institute, Limoges. His main field of interest is high-efficiency microwave PA architectures and non-linear devices characterization.
Tibault Reveyrand (M’07) received the Ph.D. degree from the University of Limoges, Limoges, France, in 2002. From 2002 to 2004, he was a Post-Doctoral Scientist with CNES (French Space Agency), Toulouse, France. Since 2005, he has been a CNRS Engineer with the XLIM Institute, University of Limoges. From 2013 to 2016, he was a Visiting Researcher with the University of Colorado, Boulder, CO, USA. His current research interests include the characterization and modeling of RF and microwave nonlinear components and devices. Dr. Reveyrand was a Technical Program Review Committee (TPRC) member of IEEE MTT-S IMS. He currently serves as a member of the IEEE MTT-11 “Microwave Measurements” Technical Committee. He has been a Reviewer for many IEEE journals. He was a recipient of the 2002 European GaAs Best Paper Award.
Philippe Bouysse was born in Aurillac, France, on September 18, 1965. He received the Ph.D. degree in communication engineering from the University of Limoges, Limoges, France, in 1992. Since 1992, he has been with the University of Limoges, Brive, France, as a Teacher and Researcher with the XLIM Laboratory. His main research interests are the modeling of microwave transistors and the design and optimization of microwave PAs
Jean-Michel Nébus received the Ph.D. degree in electronics from the University of Limoges, Limoges, France, in 1988. He was a Project Engineer with Alcatel Space Industries, Toulouse, France. He is currently a Professor with the XLIM Laboratory, University of Limoges. His main research interest is nonlinear microwave device characterization and design.
Geoffroy Soubercaze-Pun received the Ph.D. degree in electronics from the University of Toulouse, Toulouse, France, in 2007. He was with Thales Alenia Space France, where he was involved with frequency synthesis. In 2008, he joined the Centre National d’Études Spatiales (CNES), Toulouse, France. He is currently head of microwaves section in CNES. His main research interests are power amplifiers and nonlinear analysis of microwave circuits.
